Frank W Morris

US Patent:

59397381, Aug 17, 1999

Filed:

Oct 16, 1996

Appl. No.:

8/733750

Inventors:

Frank J. Morris - Plano TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 310328
H01L 310336
H01L 31072
H01L 31109

US Classification:

257197

Abstract:

A method for fabricating a bipolar transistor comprising the steps of: implanting portions 320 of a semiconductor material structure with ions to render the portions semi-insulating; forming an emitter contact region 332 at an exposed surface of a base layer 308 in a non-implanted portion of the material structure; forming an epitaxial layer of semiconductor material 322 over the exposed surface in an implanted portion of the material structure; and forming a base contact 330 over said epitaxial layer. In accordance with one embodiment of the invention, the method includes the further step of forming a second epitaxial layer of semiconductor material 324 over the first epitaxial layer 322 and then forming the base contact 330 on the second epitaxial layer 324. In accordance with another embodiment, the method includes the further step of forming a second layer of epitaxial material over the exposed surface prior to forming the epitaxial layer of semiconductor material. The base layer may be GaAs and the epitaxial of semiconductor material may be AlGaAs.

US Patent:

54593433, Oct 17, 1995

Filed:

Mar 4, 1994

Appl. No.:

8/207247

Inventors:

David J. Seymour - Plano TX
Frank J. Morris - Plano TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 2978
H01L 2980

US Classification:

257275

Abstract:

A semiconductor device which includes a channel region of predetermined conductivity type having a pair of opposing surfaces (11 or 33) , a control element of opposite conductivity type disposed on one of the opposing surfaces (13 or 31) and a pair of spaced apart electrodes (17, 19 or 35, 37) disposed over the other of the opposing surfaces. The control element and channel region form a pn junction therebetween. An electrically insulating layer (15) can be disposed between the spaced apart electrodes (17, 19) and the channel region (11) in a high frequency embodiment.

US Patent:

54851386, Jan 16, 1996

Filed:

Jun 9, 1994

Appl. No.:

8/255636

Inventors:

Frank J. Morris - Plano TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01C 1012

US Classification:

338306

Abstract:

An inverted thin film resistor structure comprises a metallic interconnect layer having predetermined patterns delineating two or more metallic interconnect leads (e. g. Al 36) overlaying a supporting layer (e. g. SiO. sub. 2 32), an interlevel dielectric layer (e. g. SiO. sub. 2 40) overlaying the supporting layer, and planarized so as to expose a top contact portion of the metallic interconnect leads, and an inverted thin film resistor (e. g. TaN 44) overlaying a portion of the planarized interlevel dielectric layer and overlaying the exposed top contact portions of the metallic interconnect leads. The novel inverted thin film resistor structure does not require a protective metal layer and does not require any vias in direct contact with the resistor. In addition, both the thin film resistor and the metallic interconnect can be formed with pattern and etch techniques.

US Patent:

53672844, Nov 22, 1994

Filed:

May 10, 1993

Appl. No.:

8/062526

Inventors:

Frank J. Morris - Plano TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01C 1012
H01L 2100

US Classification:

338306

Abstract:

An inverted thin film resistor structure comprises a metallic interconnect layer having predetermined patterns delineating two or more metallic interconnect leads (e. g. Al 36) overlaying a supporting layer (e. g. SiO. sub. 2 32), an interlevel dielectric layer (e. g. SiO. sub. 2 40) overlaying the supporting layer, and planarized so as to expose a top contact portion of the metallic interconnect leads, and an inverted thin film resistor (e. g. TaN 44) overlaying a portion of the planarized interlevel dielectric layer and overlaying the exposed top contact portion of the metallic interconnect leads. The novel inverted thin film resistor structure does not require a protective metal layer and does not require any vias in direct contact with the resistor. In addition, both the thin film resistor and the metallic interconnect can be formed with pattern and etch techniques. Improved resistor control and reliability are generally achieved since the resistor film is deposited on a substantially planar surface, and resistor length is determined by the spacing of the metallic leads rather than the size of the vias.

US Patent:

62710974, Aug 7, 2001

Filed:

Feb 4, 1999

Appl. No.:

9/244012

Inventors:

Frank J. Morris - Plano TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21331

US Classification:

438312

Abstract:

A method for fabricating a bipolar transistor comprising the steps of implanting portions 320 of a semiconductor material structure with ions to render the portions semi-insulating; forming an emitter contact region 332 at an exposed surface of a base layer 308 in a non-implanted portion of the material structure; forming an epitaxial layer of semiconductor material 322 over the exposed surface in an implanted portion of the material structure; and forming a base contact 330 over said epitaxial layer. In accordance with one embodiment of the invention, the method includes the further step of forming a second epitaxial layer of semiconductor material 324 over the first epitaxial layer 322 and then forming the base contact 330 on the second epitaxial layer 324. In accordance with another embodiment, the method includes the farther step of forming a second layer of epitaxial material over the exposed surface prior to forming the epitaxial layer of semiconductor material. The base layer may be GaAs and the epitaxial of semiconductor material may be AlGaAs.