Frank N Nelson

US Patent:

39425541, Mar 9, 1976

Filed:

Apr 19, 1974

Appl. No.:

5/462317

Inventors:

Patrick S. Werner - Costa Mesa CA
Frank L. Nelson - Mira Loma CA

Assignee:

Werner Corporation - Anaheim CA

International Classification:

B67D 502
B66C 1700
B66C 2300

US Classification:

137615

Abstract:

It is known to construct various types of cranes such as swing-boom cranes employing extendable boom sections and hammerhead cranes with rotating, counter-balanced, cantilevered booms so that conduits extend between and are connected to parts of such cranes which are movable. Such structures may be improved by using as the conduit a plurality of rigid conduit sections connected together by rotary joints permitting said conduit sections to be rotated about parallel axes. Certain of these joints are located where the conduit is connected to parts of the crane. A rotary joint is also located between each adjacent connection of the conduit to the crane. The sections are dimensioned so that during operation of the crane the rigid sections cannot be moved so as to be aligned with one another. As a consequence of this the various portions of the conduit will fold in a desirable manner as the crane is operated.

US Patent:

41830890, Jan 8, 1980

Filed:

Aug 30, 1977

Appl. No.:

5/829013

Inventors:

John W. Daughton - Perinton NY
Kenneth Gillett - Redondo Beach CA
Frank M. Nelson - Sherman Oaks CA

Assignee:

Xerox Corporation - Stamford CT

International Classification:

G06F 304
G06F 906
G03G 1500

US Classification:

364900

Abstract:

A data communications system for an electrophotographic type reproduction machine or copier. The system includes a programmable master controller with memory and a command byte generator. A plurality of secondary controllers provide input data bytes reflecting the machine status to the master controller and receive command bytes from the master controller for operating the machine components. The secondary controllers are each connected to the master controller such that corresponding data bits of the secondary controller are ORed together to provide simultaneous transmission of input data bytes from the secondary controllers to the master controller while assuring that corresponding bits of the simultaneously transmitted bytes have mutually exclusive data therein.

US Patent:

41410688, Feb 20, 1979

Filed:

Mar 24, 1977

Appl. No.:

5/780875

Inventors:

George E. Mager - Manhattan Beach CA
Frank M. Nelson - Sherman Oaks CA
Steven L. Reid - Redondo Beach CA
Philip Richardson - Pacific Palisades CA
Vernon E. Rochat - Palos Verdes CA
Donald S. Post - Fairport NY

Assignee:

Xerox Corporation - Stamford CT

International Classification:

G06F 1300

US Classification:

364200

Abstract:

An auxiliary ROM memory system which is hierarchied for providing for the contingency of additional read-only memory control program storage requirements in excess or in lieu of the predetermined ROM memory provided on-board a microprocessor based central processing unit module, and a read-only memory altering capability utilizing programmable read-only memory to expedite the implementation/installation of changes to the ROM bit patterns. The alterable PROM storage comprises bulk PROM memory including a first PROM set that is mutually exclusive as to existing on-board ROM memory for addressably branching to code extensions and/or in-line code insertions, and/or a second PROM set that is mutually inclusive as to existent on-board and contingent ROM memory for decodably addressing large-scale code overlays thereto. In addition, the alterable PROM storage comprises patch PROM for addressing, through multi-leveled decoding, small-scale code overlays to the on-board and contingent ROM memory for single in-line bit pattern alterations. Conflicting memory requests involving addresses recognized by more than one of the supra memory categories, when enabled, are presented to a predetermined hierarchy of memory precedences for resolution thereof.

US Patent:

41319443, Dec 26, 1978

Filed:

Jan 12, 1977

Appl. No.:

5/758892

Inventors:

George E. Mager - Manhattan Beach CA
Frank M. Nelson - Sherman Oaks CA
Warren L. Hall - Palos Verdes CA

Assignee:

Xerox Corporation - Stamford CT

International Classification:

G06F 1300

US Classification:

364200

Abstract:

In a control module having a central processor coupled through a system bus including data, address and control lines to access a data memory, a direct access apparatus is included coupled through the system bus to request a hold of the central processor and upon acknowledgement for directly accessing the data memory through the system bus for directing the control registers of a host machine. Also included are a diriment element interfaced to the central processor for receipt of control signals on the system bus from the direct access apparatus for hold request and for transmission of first and second control signals on the system bus from the central processor for acknowledgement, and a timed protocol unit for supervising the data, address and control signals transported on the system bus. The timed protocol unit comprises an address control coupled through the system bus to the central processor for disenabling address signals upon receipt of the first acknowledgement signal on the system bus from the diriment element, and a data control coupled through the system bus to the central processor for bidirectionally disenabling data signals upon receipt of the second acknowledge signal on the system bus from the diriment element.

US Patent:

56869150, Nov 11, 1997

Filed:

Dec 27, 1995

Appl. No.:

8/579113

Inventors:

Frank M. Nelson - Sherman Oaks CA
Thanh D. Truong - Walnut CA
Vinod Kadakia - Rancho Palos Verdes CA

Assignee:

Xerox Corporation - Stamford CT

International Classification:

H03M 740

US Classification:

341 65

Abstract:

A method of decoding Huffman-encoded words at the rate of one per clock cycle. The encoded words are formed into two strings of bits, one for odd numbered code and one for even numbered code, and two decoders in parallel are used, each first shifting in a number of coded bits during a first clock period, and converting the Huffman code to data on a second clock period. The two parallel decoders are timed so that the shift cycle of one decoder occurs at the same time as the conversion cycle of the other. Finally, the two streams of decoded data words are combined into one stream. The result is one output data word per clock cycle.

US Patent:

42837731, Aug 11, 1981

Filed:

Apr 30, 1979

Appl. No.:

6/034872

Inventors:

John W. Daughton - Perinton NY
Kenneth Gillett - Redondo Beach CA
Frank M. Nelson - Sherman Oaks CA

Assignee:

Xerox Corporation - Stamford CT

International Classification:

G06F 304
G06F 906
G03G 1500

US Classification:

364900

Abstract:

A data communications system having a programmable master controller including memory means and command byte generating means and a plurality of additional controllers providing input data bytes to the master controller and having means for receiving command bytes from the master controller. The additional controllers are each connected to the master controller such that corresponding data bits are ORed together and means are provided for the simultaneous transmission of data bytes from the additional controllers to the master controller such that corresponding bits of the simultaneously transmitted bytes have mutually exclusive data therein.

US Patent:

41375653, Jan 30, 1979

Filed:

Jan 10, 1977

Appl. No.:

5/758117

Inventors:

George E. Mager - Manhattan Beach CA
Frank M. Nelson - Sherman Oaks CA
Kenneth Gillett - Redondo Beach CA
Charles P. Holt - Palos Verdes CA
Edward L. Steiner - Macedon NY
John W. Daughton - Fairport NY
Kenton W. Fiske - Palos Verdes CA
Thomas Criswell - Venice CA
Warren L. Hall - Fairport NY

Assignee:

Xerox Corporation - Stamford CT

International Classification:

C06F 1300

US Classification:

364200

Abstract:

In a controller for a host machine such as an electrostatographic copier having a central processing unit module connected via a system bus to an input-output processing unit module, a direct memory access system functioning as part of the input-output processing unit module and operative to provide a high-speed means of refreshing and updating control registers in the host machine by direct accessing of memory in the central processing unit module. The direct memory access system may be programmed to synchronously refresh-update the host machine's control registers as in its normal mode and also asynchronously refresh-update the control registers as in the abnormal mode of a detected electrical disturbance in the electro-sensitive periphery surrounding the control registers, thus requiring restoring thereof. High-speed movement of data by the direct memory access system is achieved through dedicating a portion of random access memory in the central processing unit module for such accessing, and transferring control of the system bus from the central processing unit module to the direct memory access system. This enables data accessed through a fixed sequence of addresses from dedicated memory to be transferred directly to the host machine's control registers without incurring time constants that would otherwise be had if the data were to be manipulated by a central processor in the central processing unit module.