Fred Bailey

US Patent:

6645821, Nov 11, 2003

Filed:

Mar 20, 2002

Appl. No.:

10/102290

Inventors:

Fred D. Bailey - Irving TX
Stuart M. Jacobsen - Frisco TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 2120

US Classification:

438382, 438618, 438620, 438622

Abstract:

A thin film resistor ( ) is contained between two metal interconnect layers ( ) of an integrated circuit. Contact may be made to the resistor ( ) through vias ( ) from the metal layer ( ) above the resistor ( ) to both the thin film resistor ( ) and the underlying metal layer ( ) simultaneously. The resistor ( ) may include portions of a hard mask ( ) under the vias ( ) to protect the resistor material ( ) during the via ( ) etch. This design provides increased flexibility in fabricating the resistor ( ) since processes, materials, and chemicals do not have to satisfy the conditions of both the resistor ( ) and the rest of the integrated circuit (especially the interconnect layer ) simultaneously.

US Patent:

6921962, Jul 26, 2005

Filed:

Dec 2, 1999

Appl. No.:

09/452691

Inventors:

Fred D. Bailey - Irving TX, US
Stuart M. Jacobsen - Frisco TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L029/74
H01L031/111
H01L023/62
H01L029/00
H01L027/102

US Classification:

257537, 257154, 257359, 257380, 257381, 257577

Abstract:

A thin film resistor () is contained between two metal interconnect layers () of an integrated circuit. Contact may be made to the resistor () through vias () from the metal layer () above the resistor () to both the thin film resistor () and the underlying metal layer () simultaneously. The resistor () may include portions of a hard mask () under the vias () to protect the resistor material () during the via () etch. This design provides increased flexibility in fabricating the resistor () since processes, materials, and chemicals do not have to satisfy the conditions of both the resistor () and the rest of the integrated circuit (especially the interconnect layer ) simultaneously.

US Patent:

63262568, Dec 4, 2001

Filed:

Sep 27, 1999

Appl. No.:

9/406457

Inventors:

Fred D. Bailey - Irving TX
Stuart M. Jacobsen - Frisco TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 218234

US Classification:

438238

Abstract:

A thin film resistor processing flow solves the problem of accurately incorporating the resistor (80) to be trimmed in an optimized multilayer stack (60,70). This is achieved by measuring the total thickness of the dielectric stack (60) between the silicon substrate and the top of the dielectric stack just prior to the formation of the thin film resistor (80). Then, the thickness of the dielectric stack (60) is adjusted (60+70) to be an odd integer number of laser quarter wavelengths. The thin film resistor (60) is then formed and overlying dielectric (120) is deposited. The thickness of the overlying dielectric (120) may likewise be adjusted (120+130) to be an odd integer number of laser quarter wavelengths.