A system for monitoring Internet usage, in accordance with the present invention, includes an Internet access unit for accessing the Internet, the Internet access unit including a browser for navigating on the Internet. A transmission device is included for transmitting browser activity and providing browser activity information to be transmitted to a monitoring unit. The monitoring unit is remotely disposed from the Internet access unit and coupled to the transmission device, the monitoring unit including a display for viewing and recording Internet activity of the Internet access unit.
Peter J. Osler - Jericho VT Fred T. Tong - Hopewell Junction NY
Assignee:
International Business Machines - Armonk NY
International Classification:
G06F 1210
US Classification:
395400
Abstract:
A system providing a guess mechanism for improving the speed of translating effective addresses produced by a processor to real addresses in memory is disclosed wherein a set of Lookaside Tables and logic elements are used along with a set of validity registers and an MRU register to guess at the appropriate real frame index from one of the Tables to be output in the real address in the first cycle of a two cycle operation. The low order bits of the effective address are sent to index the Tables during the first cycle and the high order bits are used during the second cycle for comparison with the set of Table entries selected in the first cycle as containing the real frame index that is output. The selection of the actual real frame index that is output involves a guess using the validity and MRU registers along with indexing of the Tables by a portion of the low order bits. If the logic indicates, upon comparison of 1) the Table entry containing the real frame index that is output during the first cycle with 2) the high order bit comparison of the second cycle, that the selected real frame index was inappropriate, a signal is sent after the second cycle to invalidate the output of the real address incorporating that real frame index.
Peter Poon - Somers NY John Kalung Leung - Riverside CT Fred Tze-Keung Tong - Yorktown Heights NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 1700
US Classification:
39520034
Abstract:
Digitally encoded presentations are provided at the request and convenience of receivers associated with a data distribution system. The problem of reliably satisfying large numbers of randomly occurring receiver demands for digitally encoded presentations, particularly from a single storage copy of the presentation, and particularly for linear presentations, is addressed. The invention may be embodied in a system which includes a repository of digitally encoded presentations, cache memory for holding presentations which are being supplied to receivers, and a multicasting network for connecting the system to receivers. By grouping receivers into receiving groups for receiving multicasts of presentation segments, the system can satisfy the requests of any number of individual receivers, irrespective of other receivers receiving the presentation. For linear presentation, presentation segments may be defined to be of equal duration, and receiving groups may automatically be provided with sequential segments of the presentation. The system will optimally be capable of multicasting all segments of a linear presentation within a period equalling the predefined segment duration.
Functional Cache Memory Chip Architecture For Improved Cache Access
Chiao-Mei Chuang - Briarcliff Manor NY Richard E. Matick - Peekskill NY Fred T. Tong - Hopewell Junction NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 1200 G06F 1300
US Classification:
364900
Abstract:
An on-chip VLSI cache architecture including a single-port, last-select, cache array organized as an n-way set-associative cache (having n congruence classes) including a plurality of functionally integrated units on-chip in addition to the cache array and including a normal read/write CPU access function which provides an architectural organization for allowing the chip to be used in (1) a fast, "late-select" operation which may be provided with any desired degree of set-associativity while achieving an effective one-cycle write operation, and (2) a cache reload function which provides a highly parallel store-back and reload operation to substantially reduce the reload time, particularly for a store-in cache organization. The cache chip organization and architecture provide a late-select cache having a nearly transparent, multiple word reload by incorporating a Cache-Reload Buffer, a store-back buffer and a load-through function all included on the cache array chip for reloading, and a delayed write-enable for achieving an effective one-cycle write operation. Two separate decoder functions are integrated on the chip, one for cache access for normal read/write operations to and from the CPU and one for cache reload which also provides interim access to data which has been transferred out of main memory to the chip but not yet reloaded into the cache array.
Hoi Yeung Chan - Stamford CT Thomas Yu-Kiu Kwok - Washington Township NJ Fred Tze-Keung Tong - Yorktown Heights NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G08B 2300
US Classification:
3405731
Abstract:
In accordance with the present invention, a detection device capable of being coupled to a person for remotely monitoring heart and respiratory functions includes a processor, a photo cell coupled to the processor for determining blood oxygen content of the person and a temperature sensor coupled to the processor for determining a temperature of the person. The processor compares the determined blood oxygen content and the temperature to desired values. A transmitter is included for transmitting a warning signal if one of the determined blood oxygen content and the temperature are other than the desired values.