Fred D Ware

US Patent:

7356639, Apr 8, 2008

Filed:

May 18, 2004

Appl. No.:

10/848369

Inventors:

Richard Perego - Thornton CO, US
Fred Ware - Los Altos Hills CA, US
Ely Tsern - Los Altos CA, US
Craig Hampel - Los Altos CA, US

Assignee:

Rambus Inc. - Los Altos CA

International Classification:

G06F 12/00

US Classification:

711 5, 711105, 711115

Abstract:

A memory system architecture/interconnect topology includes a configurable width buffered memory module having a configurable width buffer device with at least one bypass circuit. A buffer device, such as a configurable width buffer device, is positioned between or with at least one integrated circuit memory device positioned on a substrate surface of a memory module, such as a DIMM. The configurable width buffer device is coupled to at least one memory device (by way of an internal channel), entry pin and exit pin on the memory module. The configurable width buffer device includes a multiplexer/demultiplexer circuit coupled to the entry pin and the internal channel for accessing the memory device. A bypass circuit is coupled to the entry pin and the exit pin in order to allow information to be transferred through the memory module to another coupled memory module in the memory system by way of an external channel. In an alternate embodiment of the present invention, two bypass circuits are coupled to a pair of entry and exit pins.