Frederick C Chen

US Patent:

6485869, Nov 26, 2002

Filed:

Oct 1, 1999

Appl. No.:

09/411729

Inventors:

Wilman Tsai - Saratoga CA
Marilyn Kamna - San Jose CA
Frederick Chen - San Jose CA
Jeff Farnsworth - Los Gatos CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G03F 900

US Classification:

430 5

Abstract:

An apparatus comprising a mask having an active device area and a moat. The moat substantially surrounds the mask active device area and has a width greater than a plasma specie diffusional length. A method comprising depositing a layer of resist on a mask substrate having transparent and opaque layers; and exposing the resist layer to radiation. The radiation is patterned to produce features within an active device area. The radiation is also patterned to produce a moat substantially surrounding the active device area having a width greater than a plasma specie diffusional length.

US Patent:

6692878, Feb 17, 2004

Filed:

Aug 15, 2002

Appl. No.:

10/222655

Inventors:

Wilman Tsai - Saratoga CA
Marilyn Kamna - San Jose CA
Frederick Chen - San Jose CA
Jeff Farnsworth - Los Gatos CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G03F 900

US Classification:

430 5, 355 18

Abstract:

An apparatus comprising a mask having an active device area and a moat. The moat substantially surrounds the mask active device area and has a width greater than a plasma specie diffusional length. A method comprising depositing a layer of resist on a mask substrate having transparent and opaque layers; and exposing the resist layer to radiation. The radiation is patterned to produce features within an active device area. The radiation is also patterned to produce a moat substantially surrounding the active device area having a width greater than a plasma specie diffusional length.

US Patent:

7460209, Dec 2, 2008

Filed:

Mar 28, 2005

Appl. No.:

11/092993

Inventors:

Jian Ma - San Jose CA, US
Phil Freiberger - Santa Clara CA, US
Karmen Yung - Sunnyvale CA, US
Frederick Chen - Cupertino CA, US
Chaoyang Li - San Jose CA, US
Steve Mak - Pleasanton CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G03B 27/42
G03F 1/00

US Classification:

355 53, 430 5

Abstract:

An imaging structure such as a mask or reticle may be fabricated using a patterning layer on an imaging layer. The patterning layer may have substantially different etch properties than the imaging layer. A first etch process may be selective of the patterning layer with respect to a resist layer. A second etch process may be selective of the imaging layer with respect to the patterning layer.

US Patent:

20080308527, Dec 18, 2008

Filed:

Aug 20, 2008

Appl. No.:

12/194689

Inventors:

JIAN MA - San Jose CA, US
Phil Freiberger - Santa Clara CA, US
Karmen Yung - Sunnyvale CA, US
Frederick Chen - Cupertino CA, US
Chaoyang Li - San Jose CA, US
Steve Mak - Pleasanton CA, US

Assignee:

INTEL CORPORATION - SANTA CLARA CA

International Classification:

B44C 1/22
B32B 7/02

US Classification:

216 47, 428212

Abstract:

An imaging structure such as a mask or reticle may be fabricated using a patterning layer on an imaging layer. The patterning layer may have substantially different etch properties than the imaging layer. A first etch process may be selective of the patterning layer with respect to a resist layer. A second etch process may be selective of the imaging layer with respect to the patterning layer.

US Patent:

20210074356, Mar 11, 2021

Filed:

Apr 15, 2020

Appl. No.:

16/849976

Inventors:

- Taichung City, TW
Chang-Tsung Pai - Taichung City, TW
Yu-Ting Chen - Taichung City, TW
He-Hsuan Chao - Taichung City, TW
Ming-Che Lin - Taichung City, TW
Frederick Chen - San Jose CA, US

Assignee:

Winbond Electronics Corp. - Taichung City

International Classification:

G11C 13/00

Abstract:

A data write-in method and a non-volatile memory are provided. The data write-in method includes: providing a reset voltage to a plurality of selected memory cells according to a first flag, and recursively performing a reset process for the plurality of selected memory cells; setting a second flag according to a plurality of first verification currents of the plurality of selected memory cells; and under a condition that the second flag is set: providing a set voltage to the plurality of selected memory cells according to a resistance of the plurality of selected memory cells; and setting the first flag according to a plurality of second verification currents of the plurality of selected memory cells.

US Patent:

20190027683, Jan 24, 2019

Filed:

Sep 12, 2018

Appl. No.:

16/129764

Inventors:

- Taichung City, TW
Frederick Chen - San Jose CA, US

Assignee:

Winbond Electronics Corp. - Taichung City

International Classification:

H01L 45/00
G11C 11/00
G11C 13/00
H01L 27/24

Abstract:

The resistance change memory device including a first resistance change memory element, a second resistance change memory element, and a memory controller is provided. The first resistance change memory element is disposed on a chip. The second resistance change memory element is disposed on the same chip. The memory controller is disposed on the same chip. The memory controller is configured to control data access of the first resistance change memory element and the second resistance change memory element. An accessing frequency of the first resistance change memory element is different from an accessing frequency of the second resistance change memory element.

US Patent:

20180315795, Nov 1, 2018

Filed:

Apr 28, 2017

Appl. No.:

15/499904

Inventors:

- Taichung City, TW
Frederick Chen - San Jose CA, US

Assignee:

Winbond Electronics Corp. - Taichung City

International Classification:

H01L 27/24
H01L 45/00
H01L 29/78
H01L 29/423
H01L 27/22
H01L 43/02
G11C 11/16
H01L 43/08
H01L 23/528
H01L 29/06
H01L 43/12

Abstract:

Provided are a semiconductor device including a plurality of transistors and a plurality of memory cells. Each of the transistors includes a gate structure and a source/drain region. The memory cells are respectively located over the gate structures. A lower electrode of each of the memory cells and an upper electrode of an adjacent memory cell are electrically connected to the source/drain region between corresponding two transistors.

US Patent:

20180175289, Jun 21, 2018

Filed:

Dec 15, 2016

Appl. No.:

15/379505

Inventors:

- Taichung City, TW
Frederick Chen - San Jose CA, US

Assignee:

Winbond Electronics Corp. - Taichung City

International Classification:

H01L 45/00
G11C 13/00

Abstract:

The resistance change memory device including a first resistance change memory element, a second resistance change memory element, and a memory controller is provided. The first resistance change memory element is disposed on a chip. The second resistance change memory element is disposed on the same chip. The memory controller is disposed on the same chip. The memory controller is configured to control data access of the first resistance change memory element and the second resistance change memory element. An accessing frequency of the first resistance change memory element is different from an accessing frequency of the second resistance change memory element.