Frederick A Martin

US Patent:

6519275, Feb 11, 2003

Filed:

Dec 18, 2001

Appl. No.:

10/022942

Inventors:

Neiyer S. Correal - Cooper City FL
Paul E. Gorday - West Palm Beach FL
Frederick L. Martin - Plantation FL
Qicai Shi - Coral Springs FL

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H04B 1707

US Classification:

375140, 375145, 375149, 375150

Abstract:

A system and method for orthogonal modulation of signals in communication systems. In the transmitter, differentially coded symbols are used to select time-shifted code sequences. The timing, or code position, of a code sequence is determined at the receiver by comparison to the previous code from the same channel, thus eliminating the need for dual-channel transmission and eliminating error due to differences in path propagation time. A fixed preamble code is also used to synchronize the receiver.

US Patent:

6690748, Feb 10, 2004

Filed:

Dec 21, 2001

Appl. No.:

10/036620

Inventors:

Frederick J. Martin - Plantation FL

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H04L 2714

US Classification:

375324, 375316

Abstract:

A digital IF to base band demodulator ( ) includes delta sigma samplers ( ) for sampling two channels of an IF signal at a sampling rate that is substantially higher than the Nyquist rate for the IF signal. A first pair of decimation filters ( ) decimates and filters the output of the delta sigma samplers ( ) but keeps the samples at a rate sufficient to perform digital mixing, cross adding, and pulse shape match filtering. A set of mixers ( ) mixers the output of the first pair of decimation filters with two phases of a digital representation of an local IF signal. A pair of summers ( ) sums, and subtracts outputs of the set of mixers ( ) in order to cancel undesired harmonics. A second set of decimation filters ( ) decimates and filters the output of the summers ( ) applying a filter function that is matched to a pulse shape of a base band signal present in the IF signal.

US Patent:

6774732, Aug 10, 2004

Filed:

Feb 14, 2003

Appl. No.:

10/367007

Inventors:

David B. Harnishfeger - Chandler AZ
Daniel E. Brueske - Fort Lauderdale FL
Frederick L. Martin - Plantation FL

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H03L 7085

US Classification:

331 25, 331 1 A, 331 10, 331 14, 331 16

Abstract:

A system for coarsely tuning at least one voltage controlled oscillator (VCO) ( ) in a phase locked loop (PLL) synthesizer ( ) that includes a phase-frequency detector (PFD) for determining a phase difference between a VCO frequency and a reference frequency and providing an error signal if the VCO frequency and reference frequency are at least 2 radians out of phase. A monitor ( ) is then used for tracking the number of error signals produced by the PFD. The free running frequency of the VCO may be coarsely tuned in the event the monitor circuit reaches some predetermined level. The invention offers great advantage in enabling a PLL to be coarsely tuned to enable the PLLs VCO to remain with an operational range despite operational factors that effect circuit operation.

US Patent:

6891420, May 10, 2005

Filed:

Dec 21, 2001

Appl. No.:

10/036558

Inventors:

Frederick L. Martin - Plantation FL, US
Robert E. Stengel - Pompano Beach FL, US
Jui-Kuo Juan - Coral Springs FL, US

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H04B001/40
H04B007/00

US Classification:

327260, 455 76, 4551651, 4551831, 455209, 4555501, 375327, 375373, 375376

Abstract:

A digital frequency synthesizer includes one or more reference clocks (A, A, A) optionally coupled through one or more pulse width reducers () to one or more main delay lines (B, B, B) that include a plurality of output taps (B-I, B-E). During at least certain periods of the reference clock () a plurality of the output taps are coupled to a common output (), thereby producing an output signal that has a frequency that exceeds a frequency of the one or more reference clocks. The coupling is preferably accomplished by transmission gates () that are switched by gating pulses that are received from decoders () via gating signal delay lines ().

US Patent:

6922432, Jul 26, 2005

Filed:

Mar 9, 2001

Appl. No.:

09/803258

Inventors:

Frederick L. Martin - Plantation FL, US
Qicai Shi - Coral Springs FL, US

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H04B001/69

US Classification:

375141, 375130, 375140, 375150, 370320

Abstract:

A signaling system is provided in which a spread spectrum code is cyclically shifted by a cyclical shift dictated by a bit pattern of one or more bits. The cyclically shifted spread spectrum code is used to modulate a carrier frequency, and transmitted from a transmitter to a receiver. At the receiver the signal including the cyclically shifted spectrum code is demodulated to recover the cyclically shifted code. The cyclical shift is then determined and the bit pattern which is associated with the cyclical shift is output. The method can be used in direct sequence spread spectrum communication.

US Patent:

7016661, Mar 21, 2006

Filed:

Oct 10, 2003

Appl. No.:

10/683098

Inventors:

Paul E. Gorday - West Palm Beach FL, US
Frederick L. Martin - Plantation FL, US
Qicai Shi - Coral Spings FL, US

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H04B 1/10

US Classification:

455309, 455334, 375324, 329316

Abstract:

The present invention provides a multimode receiver design for mitigation of frequency offset by selective demodulation of an input modulated signal. The receiver () comprises a plurality of demodulators (). Each of the plurality of demodulators () has the same functionality but different receiver sensitivity versus frequency-offset mitigation characteristics. Each of these demodulators incorporates a different demodulation technique. A suitable demodulator is selected to demodulate the received signal. The choice of a suitable demodulator is based on the value of the frequency offset ().

US Patent:

7050467, May 23, 2006

Filed:

Aug 7, 2000

Appl. No.:

09/633705

Inventors:

Frederick L. Martin - Plantation FL, US

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H04J 3/06
H03L 7/00

US Classification:

370517, 370503, 370518, 370519, 327141, 327161, 327162, 327163

Abstract:

A digital-to-phase or digital-to-time-shift converter () includes a delay line (), a multiplexor () and synchronization circuit (). In the converter () the clock edges of a reference signal are shifted in response to the value of a multi-bit digital word, IN (). The synchronization circuit () gates the output of the multiplexor () such that a pulse appears at the synchronization circuit's () output port () only when the circuit is gated by a signal at input TRIG (). The synchronization circuit () creates a time aperture for the multiplexor output.

US Patent:

7154978, Dec 26, 2006

Filed:

Nov 2, 2001

Appl. No.:

10/000914

Inventors:

Jui-Kuo Juan - Coral Springs FL, US
Robert E. Stengel - Pompano Beach FL, US
Frederick J. Martin - Plantation FL, US
David E. Bockelman - Dripping Springs TX, US

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H03D 3/24

US Classification:

375376, 327149

Abstract:

A delay locked loop frequency synthesizer in several embodiments uses a primary delay line element () and one or more secondary delay elements (). In one embodiment, a main delay line () is used to coarsely select a frequency output while a secondary delay element (), either passive or active, is used to increase the resolution of the primary delay line (). In the passive embodiment, a coarse and fine frequency selection is possible by selecting components from the output taps of the main delay line () as a driving signal for the passive secondary delay element () to provide the coarse adjustment and selecting an output from the secondary delay element () to provide the fine selection.