Gabriel M Tarr

US Patent:

20060041791, Feb 23, 2006

Filed:

Aug 17, 2004

Appl. No.:

10/920530

Inventors:

Walker Carroll - Waltham MA, US
Douglas Joseph - Danbury CT, US
Gabriel Tarr - Poughkeepsie NY, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - ARMONK NY

International Classification:

G06F 11/00

US Classification:

714038000

Abstract:

Debugging microcode is facilitated by a hardware assist that takes over from the microcode the basic management of handling the data for a trace entry, thereby reducing the load on the microcode to a single micro-instruction per trace operation and thereby permitting more trace points to be included in the microcode shipped to the field.

US Patent:

20090213735, Aug 27, 2009

Filed:

Feb 25, 2008

Appl. No.:

12/037065

Inventors:

Mark A. Check - Hopewell Junction NY, US
Michael Grassi - Shokan NY, US
Scot H. Rider - Pleasant Valley NY, US
Gabriel M. Tarr - Poughkeepsie NY, US

International Classification:

H04L 12/58

US Classification:

370236

Abstract:

A system to improve data packet routing in a data processing device may include a plurality of functional modules, and communication buses connecting the functional modules. The system may also include a flow control mechanism in which command packets that traverse the communication buses are each assigned their own channel with their own pool of credits. The system may further include a switch to route data packets on the communication buses from one of the functional modules to any other of the functional modules based upon the credits. In addition, any of the functional modules without credits to send the data packets on a particular channel may send a message to have the switch perform a route test.

US Patent:

20190086982, Mar 21, 2019

Filed:

Sep 12, 2018

Appl. No.:

16/129417

Inventors:

- San Diego CA, US
SeyedMajid Zahedi - Durham NC, US
Derek Robert Hower - Durham NC, US
Carl Alan Waldspurger - Palo Alto CA, US
Jeffrey Todd Bridges - Raleigh NC, US
Sanjay Bhikhubhai Patel - Cary NC, US
Gabriel Martel Tarr - Durham NC, US
Chih Kang Lin - Raleigh NC, US
Ryan Donovan Wells - Raleigh NC, US

International Classification:

G06F 1/32

Abstract:

Allocating power between multiple central processing units (CPUs) in a multi-CPU processor based on total current availability and individual CPU quality-of-service (QoS) requirements is disclosed. Current from a power rail is allocated to CPUs by a global current manger (GCM) circuit related to performance criteria set by CPUs. The CPUs can request increased current allocation from the GCM circuit, such as in response to executing a higher performance task. If the increased current allocation request keeps total current on the power rail within its maximum rail current limit, the GCM circuit approves the request to allow the CPU increased current allocation. This can allow CPUs executing higher performance tasks to have a larger current allocation than CPUs executing lower performance tasks without the maximum rail current limit being exceeded, and without having to necessarily lower voltage of the power rail, which could unnecessarily lower performance of all CPUs.

US Patent:

20190012268, Jan 10, 2019

Filed:

Jul 6, 2017

Appl. No.:

15/642756

Inventors:

- Armonk NY, US
Michael Grassi - Shokan NY, US
Howard M. Haynie - Wappingers Falls NY, US
Raymond M. Higgs - Poughkeepsie NY, US
Luke M. Hopkins - Peterborough NH, US
Kirk Pospesel - Yorktown Heights NY, US
Gabriel M. Tarr - Durham NC, US

International Classification:

G06F 12/10
G06F 3/06

Abstract:

A system for managing one or more queues in a multi-processor environment includes a shared memory configured to be accessed by a plurality of processing elements, and a queue manager configured to control a queue in the shared memory, the queue manager storing dynamically configurable queue parameters including an operation address associated with the queue, a number of queue elements and a size of each queue element. The queue manager is configured to intercept a message from a processing element, the message directed to the shared memory and specifying the operation address, calculate an address of a location in the shared memory corresponding to one or more available queue elements, the calculating performed based on the operation address, the number of queue elements, and the size of each queue element, and perform one or more queuing operations on the queue based on the calculated address.

US Patent:

20190012269, Jan 10, 2019

Filed:

Nov 7, 2017

Appl. No.:

15/805384

Inventors:

- Armonk NY, US
Michael Grassi - Shokan NY, US
Howard M. Haynie - Wappingers Falls NY, US
Raymond M. Higgs - Poughkeepsie NY, US
Luke M. Hopkins - Peterborough NH, US
Kirk Pospesel - Yorktown Heights NY, US
Gabriel M. Tarr - Durham NC, US

International Classification:

G06F 12/10
G06F 3/06

Abstract:

A system for managing one or more queues in a multi-processor environment includes a shared memory configured to be accessed by a plurality of processing elements, and a queue manager configured to control a queue in the shared memory, the queue manager storing dynamically configurable queue parameters including an operation address associated with the queue, a number of queue elements and a size of each queue element. The queue manager is configured to intercept a message from a processing element, the message directed to the shared memory and specifying the operation address, calculate an address of a location in the shared memory corresponding to one or more available queue elements, the calculating performed based on the operation address, the number of queue elements, and the size of each queue element, and perform one or more queuing operations on the queue based on the calculated address.

US Patent:

20180267909, Sep 20, 2018

Filed:

Mar 15, 2017

Appl. No.:

15/459612

Inventors:

- Armonk NY, US
Clinton E. Bubb - Pleasant Valley NY, US
Michael Grassi - Shokan NY, US
Howard M. Haynie - Wappingers Falls NY, US
Raymond M. Higgs - Poughkeepsie NY, US
Luke M. Hopkins - Peterborough NH, US
Kirk Pospesel - Yorktown NY, US
Gabriel M. Tarr - Durham NC, US

International Classification:

G06F 13/16

Abstract:

A system for managing one or more queues in a multi-processor environment includes a queue manager disposed in communication with a plurality of processors and a memory shared by the plurality of processors, and a queue configured to be controlled by the queue manager, the queue including independent and discrete queue elements and having a starting location specified by a base address, the queue manager having one or more dynamically configurable parameters, the one or more dynamically configurable parameters including a size of each of the queue elements. The queue manager is configured to perform receiving a message from a processor of the plurality of processors, the message including an operation address specifying a fixed storage location in the memory and a request related to accessing the memory, selecting the queue based on the operation address, and performing a queuing operation on the queue based on the request.

US Patent:

20180088950, Mar 29, 2018

Filed:

Sep 28, 2016

Appl. No.:

15/278265

Inventors:

- Armonk NY, US
Luke M. Hopkins - Peterborough NH, US
Mushfiq U. Saleheen - Poughkeepsie NY, US
Gabriel M. Tarr - Durham NC, US

International Classification:

G06F 9/30
G06F 15/82

Abstract:

Technical solutions are described for a supervisory processor to pass an out-of-band communication to a target processor in a multiprocessor system. For example, a first processor in a multi-processor system includes a register configured to store a command from a second processor of the multi-processor system, and to store a response to the command from the second processor. The first processor determines that the second processor has issued the command for execution by the first processor based on a first portion of the register being set to a first state, which is a predetermined state. The first processor also, responsively, reads the command from the second processor by parsing a second portion of the register. The first processor includes executes the command and stores the response for the command in the register.

US Patent:

20170344102, Nov 30, 2017

Filed:

May 24, 2017

Appl. No.:

15/604038

Inventors:

- San Diego CA, US
Jeffrey Todd Bridges - Raleigh NC, US
Sanjay Patel - Cary NC, US
Shraddha Sridhar - Raleigh NC, US
Burt Lee Price - Apex NC, US
Gabriel Martel Tarr - Durham NC, US

International Classification:

G06F 1/32
H02M 1/08

Abstract:

Adaptive voltage modulation circuits for adjusting supply voltage to reduce supply voltage droops and minimize power consumption are provided. In one aspect, an adaptive voltage modulation circuit detects a supply voltage droop by detecting when a supply voltage falls below a droop threshold voltage, and adjusts a clock signal provided to a load circuit in response to a supply voltage droop. The adaptive voltage modulation circuit keeps a count of the number of clock signal cycles during which the supply voltage is below the droop threshold voltage. The adaptive voltage modulation circuit increases the supply voltage in response to the count exceeding an upper threshold value, and decreases the supply voltage in response to the count being less than a lower threshold value at an end of a defined period. The adaptive voltage modulation circuit can reduce the time a load circuit operates with reduced frequency while minimizing power consumption.