Gail Diane Shelton

US Patent:

6358819, Mar 19, 2002

Filed:

Dec 15, 1998

Appl. No.:

09/212315

Inventors:

Gail D. Shelton - Colorado Springs CO
Gayle W. Miller - Colorado Springs CO

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H01L 2176

US Classification:

438433, 438440, 438449, 438283, 438287, 148DIG 163

Abstract:

An improved dual gate oxide process for dual-gated devices using oxygen ion implantation to vary the thickness of gate oxide layers. The desired layers are identified by photoresist layer patterning prior to an ion implantation. A subsequent heat treatment oxidizes the implanted region.

US Patent:

6383332, May 7, 2002

Filed:

May 31, 2000

Appl. No.:

09/583434

Inventors:

Gail D. Shelton - Colorado Springs CO
Gayle W. Miller - Colorado Springs CO

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H01L 21302

US Classification:

156345, 451 66, 451 39, 451259, 451282, 51306, 216 84, 216 88, 216 89, 216 90, 216 93, 216 95

Abstract:

A method of planarizing a semiconductor wafer having a polishing endpoint layer that includes a ligand is disclosed. One step of the method includes polishing a first side of the wafer in order to remove the ligand from the wafer. Another step of the method includes determining that a chelating agent has bound the ligand due to the polishing step removing the ligand of the polishing endpoint layer. The method also includes the step of terminating the polishing step in response to determining that the chelating agent has bound the ligand. A polishing system is also disclosed which detects a polishing endpoint based upon a chelating agent binding a ligand of a polishing endpoint layer of a semiconductor device.

US Patent:

6509520, Jan 21, 2003

Filed:

Jun 7, 1995

Appl. No.:

08/487820

Inventors:

Robert Joseph Stephen Kyle - Rowlett TX
Gail D. Shelton - Albuquerque NM
Sam McKenney - Dallas TX

Assignee:

Raytheon Company - Lexington MA

International Classification:

H01L 3534

US Classification:

136201, 136203, 136233, 62 32

Abstract:

A high-strength, single-staged, composite thermoelectric cooler ( ) for stabilizing the temperature of an uncooled, infrared detector ( ) comprising a pair of ceramic plates ( ), a plurality of thermoelectric elements ( ) sandwiched between the plates ( ) such that the thermoelectric elements ( ) and the ceramic plates ( ) define a plurality of chambers ( ), and a thermoelectric insulator ( ) which substantially fills the chambers ( ) inside the thermoelectric cooler ( ) forming a high-strength composite structure with the thermoelectric elements ( ) and the ceramic plates ( ).

US Patent:

6527867, Mar 4, 2003

Filed:

May 30, 2000

Appl. No.:

09/580939

Inventors:

Kunal Taravade - Colorado Springs CO
Gayle Miller - Colorado Springs CO
Gail Shelton - Colorado Springs CO

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

C23C 1690

US Classification:

118720, 438780, 430311

Abstract:

A method of fabricating an integrated circuit using photolithography and an antireflective coating. An antireflective coating is formed on a substrate wherein the antireflective coating is electrically polarizable. A photoresist coating is formed on the antireflective coating on a side opposite from the substrate and the photoresist is exposed to activating radiation. The antireflective coating is subjected to an applied electric field at substantially the same time as the photoresist is exposed to activating radiation. The radiation absorption coefficient of said antireflective coating is increased and the refractive index of said antireflective coating is changed to be substantially equal to the refractive index of said photoresist coating.

US Patent:

6614097, Sep 2, 2003

Filed:

Sep 30, 1998

Appl. No.:

09/164069

Inventors:

Gayle W. Miller - Colorado Springs CO
Gail D. Shelton - Colorado Springs CO

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H01L 2358

US Classification:

257637, 257760, 438763, 438780

Abstract:

A method for composing a dielectric layer within an interconnect structure of a multilayer semiconductor device is disclosed. A layer of silica precursor material is first deposited on a silicon substrate. Without affecting its structure and porosity, the layer of silica precursor material is then dried; and the layer of silica precursor material becomes porous silica film. Subsequently, a protective layer, such as parylene, is deposited on top of the dried porous silica film. The thickness of the protective layer should be greater than the peak-valley planarization requirements of the silicon substrate surface. As a result, a composite porous silica film, which services as a dielectric layer within an interconnect structure, is formed. This composite porous silica film has a relatively low dielectric constant and is able to withstand damage from a standard CMP procedure.

US Patent:

6806162, Oct 19, 2004

Filed:

Jun 11, 2003

Appl. No.:

10/459072

Inventors:

Gayle W. Miller - Colorado Springs CO
Gail D. Shelton - Colorado Springs CO

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H01L 2176

US Classification:

438409, 438635, 438637, 438642, 438762, 438780

Abstract:

A method for composing a dielectric layer within an interconnect structure of a multilayer semiconductor device is disclosed. A layer of silica precursor material is first deposited on a silicon substrate. Without affecting its structure and porosity, the layer of silica precursor material is then dried; and the layer of silica precursor material becomes porous silica film. Subsequently, a protective layer, such as parylene, is deposited on top of the dried porous silica film. The thickness of the protective layer should be greater than the peak-valley planarization requirements of the silicon substrate surface. As a result, a composite porous silica film, which services as a dielectric layer within an interconnect structure, is formed. This composite porous silica film has a relatively low dielectric constant and is able to withstand damage from a standard CMP procedure.

US Patent:

20010051403, Dec 13, 2001

Filed:

May 23, 2001

Appl. No.:

09/863979

Inventors:

Gayle Miller - Colorado Springs CO, US
Gail Shelton - Colorado Springs CO, US

International Classification:

H01L021/8238

US Classification:

438/202000

Abstract:

A method and apparatus for forming a dielectric layer. A dielectric precursor solution is deposited onto a surface of a substrate. The substrate is spun to spread the dielectric precursor solution over the surface of the substrate. A catalyst is introduced through a filter, wherein the filter causes a substantially homogenous distribution of the catalyst within the substrate, wherein a dielectric layer forms containing pores and wherein a solvent is contained in the pores. The solution is dried to form the dielectric layer using a carrier gas after introducing the catalyst, wherein the carrier gas places a positive pressure within the pores while removing the solvent to form a low-k dielectric layer.

US Patent:

20020058382, May 16, 2002

Filed:

Dec 21, 2001

Appl. No.:

10/026282

Inventors:

Gail Shelton - Colorado Springs CO, US
Gayle Miller - Colorado Springs CO, US

International Classification:

H01L021/8238
H01L021/8234
H01L021/336
H01L021/76

US Classification:

438/275000, 438/287000, 438/407000, 438/216000

Abstract:

An improved dual gate oxide process for dual-gated devices using oxygen ion implantation to vary the thickness of gate oxide layers. The desired layers are identified by photoresist layer patterning prior to an ion implantation. A subsequent heat treatment oxidizes the implanted region.