Gail Vallery Shelton

US Patent:

6509520, Jan 21, 2003

Filed:

Jun 7, 1995

Appl. No.:

08/487820

Inventors:

Robert Joseph Stephen Kyle - Rowlett TX
Gail D. Shelton - Albuquerque NM
Sam McKenney - Dallas TX

Assignee:

Raytheon Company - Lexington MA

International Classification:

H01L 3534

US Classification:

136201, 136203, 136233, 62 32

Abstract:

A high-strength, single-staged, composite thermoelectric cooler ( ) for stabilizing the temperature of an uncooled, infrared detector ( ) comprising a pair of ceramic plates ( ), a plurality of thermoelectric elements ( ) sandwiched between the plates ( ) such that the thermoelectric elements ( ) and the ceramic plates ( ) define a plurality of chambers ( ), and a thermoelectric insulator ( ) which substantially fills the chambers ( ) inside the thermoelectric cooler ( ) forming a high-strength composite structure with the thermoelectric elements ( ) and the ceramic plates ( ).

US Patent:

55720595, Nov 5, 1996

Filed:

Jun 7, 1995

Appl. No.:

8/477718

Inventors:

William K. Walker - Plano TX
Steven N. Frank - McKinney TX
Charles M. Hanson - Richardson TX
Robert J. S. Kyle - Rowlett TX
Edward G. Meissner - Dallas TX
Robert A. Owen - Rowlett TX
Gail D. Shelton - Mesquite TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 27095

US Classification:

257448

Abstract:

A thermal isolation structure (10) is disposed between a focal plane array and an integrated circuit substrate (12). The thermal isolation structure (10) includes a mesa-type formation (16) and a mesa strip conductor (18, 26) extending from the top of the mesa-type formation (16) to an associated contact pad (14) on the integrated circuit substrate (12). After formation of the mesa-type formation (16) and the mesa strip conductor (18, 26), an anisotropic etch using the mesa strip conductor (18, 26) as an etch mask removes excess mesa material to form trimmed mesa-type formation (24) for improved thermal isolation. Bump bonding material (20) may be deposited on mesa strip conductor (18, 26) and can also be used as an etch mask during the anisotropic etch. Thermal isolation structure (100) can include mesa-type formations (102), each with a centrally located via (110) extending vertically to an associated contact pad (104) of integrated circuit substrate (106). A conductor (108) is deposited on top of mesa-type formation (102), along the walls of via (110), and overlaying contact pad (104).

US Patent:

62582054, Jul 10, 2001

Filed:

Mar 24, 2000

Appl. No.:

9/534652

Inventors:

Brynne K. Chisholm - Garland TX
Gayle W. Miller - Colorado Springs CO
Gail D. Shelton - Colorado Springs CO

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H01L 21302

US Classification:

156345

Abstract:

An apparatus for planarizing a semiconductor wafer having a polishing endpoint layer that includes a catalyst material is disclosed. The apparatus is operable to detect the endpoint based upon the chemical slurry whether a catalytic reaction has occurred due to the polishing platen removing a portion of the catalyst material from the wafer.

US Patent:

55742823, Nov 12, 1996

Filed:

Jun 30, 1994

Appl. No.:

8/268365

Inventors:

William K. Walker - Plano TX
John P. Long - Garland TX
Robert A. Owen - Rowlett TX
Bert T. Runnels - Garland TX
Gail D. Shelton - Mesquite TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G01J 506

US Classification:

2503383

Abstract:

A hybrid thermal detector (10, 110) includes a focal plane array (20, 120), a thermal isolation structure (40, 140), and an integrated circuit substrate (60, 160). The focal plane array (20, 120) includes thermal sensors (30, 130). The thermal isolation structure (40, 140) includes untrimmed mesa-type formations (44, 146, 148) and mesa strip conductors (42, 142, 144) that provide thermal isolation, signal transport, and structural support of the focal plane array (20, 120) when mounted on the integrated circuit substrate (60, 160). Hybrid thermal detector (10) includes a common electrode (28) which provides a bias voltage to all thermal sensors (30). Hybrid thermal detector (110) has electrically isolated thermal sensors (130), each thermal sensor (130) is supported by mesa strip conductors (142, 144), which provide a bias voltage to and receive a signal voltage from the thermal sensor (130). To improve both pixel-substrate and inter-pixel thermal isolation, mesa strip conductors (42, 142, 144) and common electrode (28) may be formed from a thermally insulating material, such as cermet or a semiconductive material. Untrimmed mesa-type formations (44, 146, 148) may be anisotropically etched to remove excess mesa material and improve pixel-substrate thermal isolation.

US Patent:

54245443, Jun 13, 1995

Filed:

Apr 29, 1994

Appl. No.:

8/235835

Inventors:

Gail D. Shelton - Mesquite TX
James F. Belcher - Plano TX
Steven N. Frank - McKinney TX
Charles M. Hanson - Richardson TX
Edward G. Meissner - Dallas TX
Robert A. Owen - Rowlett TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H04N 533

US Classification:

250332

Abstract:

A thermal detection system (100, 200) includes a focal plane array (102, 202), a thermal isolation structure (104, 204) and an integrated circuit substrate (106, 206). The focal plane array (102, 202) includes thermal sensors (114, 214) formed from a pyroelectric element (116, 216), such as barium strontium titanate (BST). One side of the pyroelectric element (116, 216) is coupled to a contact pad (110, 210) disposed on the integrated circuit substrate (106, 206) through a mesa strip conductor (112, 212) of the thermal isolation structure (104, 204). The other side of the pyroelectric element (116, 216) is coupled to a common electrode (120, 220). In one embodiment, slots (128) are formed in the common electrode (120) intermediate the thermal sensors (114) to improve inter-pixel thermal isolation. In another embodiment, slots (236) are formed in the optical coating (224) to improve inter-pixel thermal isolation. The common electrode (120, 220) may be formed from a thermally insulating material, such as a silicon monoxide and chromium matrix (cermet) or other metal oxide.

US Patent:

54263034, Jun 20, 1995

Filed:

Apr 29, 1994

Appl. No.:

8/235068

Inventors:

Robert A. Owen - Rowlett TX
John P. Long - Garland TX
Bert T. Runnels - Garland TX
Gail D. Shelton - Mesquite TX
William K. Walker - Plano TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H04N 533

US Classification:

250332

Abstract:

A thermal detection system (10, 110, 210) includes a focal plane array (20, 120, 220), a thermal isolation structure (40, 140, 240), and an integrated circuit substrate (60, 160, 260). The focal plane array (20, 120, 220) includes a plurality of thermal sensors (30, 130, 230). The thermal isolation structure (40, 140, 240) includes mesa-type formations (44, 146, 148, 244) and bridge structures (42, 142, 144, 242) that provide thermal isolation, signal transport, and structural support of the focal plane array (20, 120, 220) when mounted on the integrated circuit substrate (60, 160, 260). Thermal detection system (10) includes an infrared absorber and common electrode assembly (22) which provides a bias voltage to all thermal sensors (30). Thermal detection system (110) has a plurality of electrically isolated thermal sensors (130), each thermal sensor (130) is supported by bridge structures (142, 144), which provide a bias voltage to and receive a signal voltage from the thermal sensor (130). Thermal detection system ( 220) has a plurality of electrically isolated thermal sensors (230), each thermal sensor (230) is electrically coupled to a pair of leads (246, 247), which are supported by a reinforcing layer (245).

US Patent:

60718188, Jun 6, 2000

Filed:

Jun 30, 1998

Appl. No.:

9/109331

Inventors:

Brynne K. Chisholm - Garland TX
Gayle W. Miller - Colorado Springs CO
Gail D. Shelton - Colorado Springs CO

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H01L 21302

US Classification:

438692

Abstract:

A method of planarizing a semiconductor wafer having a polishing endpoint layer that includes a catalyst material is discloes. One step of the method includes polishing a first side of the wafer in order to remove material from the wafer. Another step of the method includes determining that a catalytic reaction has occurred due to the polishing step removing the catalyst material of the polishing endpoint layer. The method also includes the step of terminating the polishing step in response to determining that the catalytic reaction has occurred. A polishing system is also disclosed which detects a polishing endpoint based upon a catalytic reaction triggered by a catalyst material of a polishing endpoint layer of a semiconductor device.

US Patent:

56538510, Aug 5, 1997

Filed:

Jul 5, 1994

Appl. No.:

8/270870

Inventors:

Gail D. Shelton - Mesquite TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21302

US Classification:

216 67

Abstract:

A method to anisotropically etch a titanate wafer (16 or 39) is provided. The method includes the steps of generating a plasma (32) and mixing an organic acid reagent with the plasma (32). The titanate wafer (16 or 39) is then exposed to the plasma (32) and organic acid reagent mixture thereby etching (42) the titanate wafer (16 or 39).