Gangfeng F Ye

age ~48

from San Jose, CA

Also known as:
  • Gangfeng Te Ye
  • Gang F Ye
  • Ye Gangfeng
Phone and address:
10094 Roseview Dr, San Jose, CA 95127

Gangfeng Ye Phones & Addresses

  • 10094 Roseview Dr, San Jose, CA 95127
  • Morgan Hill, CA
  • s
  • 219 Caraway Ln, Cary, NC 27519
  • Pittsburg, CA
  • Fulton, CA
  • Fremont, CA
  • East Lansing, MI
  • Alameda, CA

Us Patents

  • Gan Lateral Vertical Jfet With Regrown Channel And Dielectric Gate

    view source
  • US Patent:
    20200111878, Apr 9, 2020
  • Filed:
    Dec 6, 2019
  • Appl. No.:
    16/705833
  • Inventors:
    Gangfeng Ye - Fremont CA, US
  • International Classification:
    H01L 29/20
    H01L 29/66
    H01L 29/10
    H01L 29/78
    H01L 29/808
    H01L 29/08
    H01L 29/417
    H01L 29/778
  • Abstract:
    A vertical JFET is provided. The JFET is mixed with lateral channel structure and p-GaN gate structure. The JFET has a N+ implant source region. In one embodiment, a JFET is provided with a drain metal deposited over a backside of an N substrate, an n-type drift layer epitaxial grown over a topside of the N substrate, a buried P-type block layer deposited over the n-type drift layer, an implanted N+ source region on side walls of the lateral channel layer, and an source metal attached to the top of the p-layer and attached to the implanted N+ source region at the side. In one embodiment, the JFET further comprises a gate layer, and wherein the gate layer is a dielectric gate structure that enables a fully enhanced channel. In another embodiment, the gate layer is a p-type GaN gate structure that enables a partially enhanced channel.
  • High Power Gallium Nitride Electronics Using Miscut Substrates

    view source
  • US Patent:
    20190348522, Nov 14, 2019
  • Filed:
    May 28, 2019
  • Appl. No.:
    16/423414
  • Inventors:
    - Santa Clara CA, US
    Dave P. Bour - Cupertino CA, US
    Thomas R. Prunty - Santa Clara CA, US
    Gangfeng Ye - Fremont CA, US
  • Assignee:
    NEXGEN POWER SYSTEMS, INC. - Santa Clara CA
  • International Classification:
    H01L 29/66
    H01L 21/02
    H01L 29/04
    H01L 29/861
    H01L 21/76
    H01L 29/06
    H01L 29/20
  • Abstract:
    A method of fabricating an electronic device includes providing a III-V substrate having a hexagonal crystal structure and a normal to a growth surface characterized by a misorientation from the direction of between 0.15 and 0.65. The method also includes growing a first III-V epitaxial layer coupled to the III-V substrate and growing a second III-V epitaxial layer coupled to the first III-V epitaxial layer. The method further includes forming a first contact in electrical contact with the III-V substrate and forming a second contact in electrical contact with the second III-V epitaxial layer.
  • Gan Lateral Vertical Hjfet With Source-P Block Contact

    view source
  • US Patent:
    20180219071, Aug 2, 2018
  • Filed:
    Jan 29, 2018
  • Appl. No.:
    15/882017
  • Inventors:
    - Jiangsu, CN
    Gangfeng Ye - Fremont CA, US
  • International Classification:
    H01L 29/20
    H01L 29/66
    H01L 29/808
    H01L 29/205
  • Abstract:
    A vertical JFET is provided. The JFET is mixed with lateral channel structure and p-GaN gate structure. The JFET has an improved barrier layer for p-GaN block layer and enhanced Ohmic contact with source. In one embodiment, regrowth of lateral channel is provided so that counter doping surface Mg will be buried. In another embodiment, a dielectric layer is provided to protect p-type block layer during the processing, and later make Ohmic source and p-type block layer. Method of a barrier regrown layer for enhanced lateral channel performance is provided where a regrown barrier layer is deposited over the drift layer. The barrier regrown layer is an anti-p-doping layer. Method of a patterned regrowth for enhanced Ohmic contact is provided where a patterned masked is used for the regrowth.
  • Gan Lateral Vertical Jfet With Regrown Channel And Dielectric Gate

    view source
  • US Patent:
    20180219072, Aug 2, 2018
  • Filed:
    Jan 29, 2018
  • Appl. No.:
    15/882040
  • Inventors:
    - Jiangsu, CN
    Gangfeng Ye - Fremont CA, US
  • International Classification:
    H01L 29/20
    H01L 29/66
    H01L 29/78
    H01L 29/808
    H01L 29/10
  • Abstract:
    A vertical JFET is provided. The JFET is mixed with lateral channel structure and p-GaN gate structure. The JFET has a N+ implant source region. In one embodiment, a JFET is provided with a drain metal deposited over a backside of an N substrate, an n-type drift layer epitaxial grown over a topside of the N substrate, a buried P-type block layer deposited over the n-type drift layer, an implanted N+ source region on side walls of the lateral channel layer, and an source metal attached to the top of the p-layer and attached to the implanted N+ source region at the side. In one embodiment, the JFET further comprises a gate layer, and wherein the gate layer is a dielectric gate structure that enables a fully enhanced channel. In another embodiment, the gate layer is a p-type GaN gate structure that enables a partially enhanced channel.
  • High Power Gallium Nitride Electronics Using Miscut Substrates

    view source
  • US Patent:
    20180166556, Jun 14, 2018
  • Filed:
    Sep 6, 2017
  • Appl. No.:
    15/697161
  • Inventors:
    - Los Altos Hills CA, US
    Dave P. Bour - Cupertino CA, US
    Thomas R. Prunty - Santa Clara CA, US
    Gangfeng Ye - Fremont CA, US
  • Assignee:
    Nexgen Power Systems, Inc. - Los Altos Hills CA
  • International Classification:
    H01L 29/66
    H01L 21/02
    H01L 29/04
    H01L 29/06
    H01L 29/20
    H01L 29/861
  • Abstract:
    A method of fabricating an electronic device includes providing a III-V substrate having a hexagonal crystal structure and a normal to a growth surface characterized by a misorientation from the direction of between 0.15 and 0.65. The method also includes growing a first III-V epitaxial layer coupled to the III-V substrate and growing a second III-V epitaxial layer coupled to the first III-V epitaxial layer. The method further includes forming a first contact in electrical contact with the III-V substrate and forming a second contact in electrical contact with the second III-V epitaxial layer.
  • High Power Gallium Nitride Electronics Using Miscut Substrates

    view source
  • US Patent:
    20170133481, May 11, 2017
  • Filed:
    May 17, 2016
  • Appl. No.:
    15/156979
  • Inventors:
    - San Jose CA, US
    Dave P. Bour - Cupertino CA, US
    Thomas R. Prunty - Santa Clara CA, US
    Gangfeng Ye - Fremont CA, US
  • International Classification:
    H01L 29/66
    H01L 21/02
    H01L 29/06
    H01L 29/04
    H01L 29/861
    H01L 29/20
  • Abstract:
    A method of fabricating an electronic device includes providing a III-V substrate having a hexagonal crystal structure and a normal to a growth surface characterized by a misorientation from the direction of between 0.15 and 0.65. The method also includes growing a first III-V epitaxial layer coupled to the III-V substrate and growing a second III-V epitaxial layer coupled to the first III-V epitaxial layer. The method further includes forming a first contact in electrical contact with the III-V substrate and forming a second contact in electrical contact with the second III-V epitaxial layer.
  • High Power Gallium Nitride Electronics Using Miscut Substrates

    view source
  • US Patent:
    20150123138, May 7, 2015
  • Filed:
    Nov 4, 2013
  • Appl. No.:
    14/071032
  • Inventors:
    - San Jose CA, US
    David P. Bour - Cupertino CA, US
    Thomas R. Prunty - Santa Clara CA, US
    Gangfeng Ye - Fremont CA, US
  • Assignee:
    AVOGY, INC. - San Jose CA
  • International Classification:
    H01L 29/20
    H01L 29/66
    H01L 29/861
    H01L 21/02
    H01L 21/76
  • US Classification:
    257 76, 438478, 438400
  • Abstract:
    An electronic device includes a III-V substrate having a hexagonal crystal structure and a normal to a growth surface characterized by a misorientation from the direction of between 0.15 and 0.65. The electronic device also includes a first epitaxial layer coupled to the III-V substrate and a second epitaxial layer coupled to the first epitaxial layer. The electronic device further includes a first contact in electrical contact with the substrate and a second contact in electrical contact with the second epitaxial layer.

Facebook

Gangfeng Ye Photo 1

Gangfeng Ye

view source

Get Report for Gangfeng F Ye from San Jose, CA, age ~48
Control profile