Gary R Ellis

US Patent:

7020861, Mar 28, 2006

Filed:

Jul 17, 2003

Appl. No.:

10/621950

Inventors:

Charles Jay Alpert - Round Rock TX, US
Gary Robert Ellis - Austin TX, US
Gi-Joon Nam - Austin TX, US
Paul Gerard Villarrubia - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 17/50

US Classification:

716 6, 716 8, 716 9, 716 10, 716 12

Abstract:

A method of designing an integrated circuit including executing a placement algorithm to place a set of objects within the integrated circuit. The set of objects includes latched objects and non-latched objects. The algorithm places objects to minimize clock signal delay subject to a constraint on the placement distribution of the latched objects relative to the placement distribution of the non-latched objects. The latched object and non-latched object placement constraints may limit the difference between the latched object center of mass and a non-latched object center of mass. The latched object center of mass equals a sum of size-location products for each latched object divided by the sum of sizes for each latched object. The constraints may require that the latched object center of mass and the non-latched center of mass both equal the center of mass for all objects.