Ashish Pancholy - Santa Clara CA Gary A. Gibbs - San Jose CA
Assignee:
Cypress Semiconductor Corporation - San Jose CA
International Classification:
H03K 190175
US Classification:
326 81, 326 62, 326 63, 326 68, 326 80
Abstract:
An integrated circuit device includes an input circuit; logic circuitry coupled to the input circuit; an output circuit coupled to the logic circuitry; and a select circuit coupled to the input circuit, output circuit and logic circuitry. The select circuit generates a select signal that causes the input circuit, output circuit and logic circuit to operate according to a first state or a second state. The output buffer is configured to receive the select signal which selects output buffer operation at the first state or the second state. The output buffer is also configured to maintain a constant slew rate while operating in either the first or second state.
Programmable Transmission Line Impedance Matching Circuit
Gary Gibbs - San Jose CA Manoj B. Roge - San Jose CA
Assignee:
Cypress Semiconductor Corp. - San Jose CA
International Classification:
H03K 190175
US Classification:
326 30, 326 83, 326 87
Abstract:
An apparatus comprising a first circuit, a second circuit, and an output circuit. The first circuit may be configured to generate a first digital output in response to (i) a reference input and (ii) a feedback input. The second circuit may be configured to generate a second digital output in response to (i) the first digital output and (ii) a second feedback input. The output circuit may be configured to generate a third output in response to a data input, wherein an output impedance of the output circuit is adjusted in response to (i) the first digital output and (ii) the second digital output.
Multi-Level Programmable Voltage Control And Output Buffer With Selectable Operating Voltage
Ashish Pancholy - Santa Clara CA Gary A. Gibbs - San Jose CA
Assignee:
Cypress Semiconductor Corporation - San Jose CA
International Classification:
H03K 190175
US Classification:
326 81, 326 83
Abstract:
An integrated circuit device includes an input circuit; logic circuitry coupled to the input circuit; an output circuit coupled to the logic circuitry; and a select circuit coupled to the input circuit, output circuit and logic circuitry. The select circuit generates a select signal that causes the input circuit, output circuit and logic circuit to operate according to a first state or a second state. The output buffer is configured to receive the select signal which selects output buffer operation at the first state or the second state. The output buffer is also configured to maintain a constant slew rate while operating in either the first or second state.
Method And System For High Resolution Delay Lock Loop
Gary Gibbs - San Jose CA Lingsong Xu - Newark CA Sanjay Sancheti - Starkville MS
Assignee:
Cypress Semiconductor Corporation - San Jose CA
International Classification:
H03L 706
US Classification:
327158, 327161
Abstract:
A method for utilizing a delay lock loop to cover a wide delay range. In one method embodiment, the present invention receives a reference clock pulse. Next, in a first loop, a phase variation is adjusted between the feedback clock pulse and the reference clock pulse utilizing a coarse delay in conjunction with a first fine delay. The resulting pulse is then output to a chip delay and then sent back to the delay lock loop as a feedback clock pulse. Additionally, in a second loop, the phase variation is adjusted between said second loop and said first loop utilizing the coarse delay in conjunction with a second fine delay, wherein the second fine delay has a delay range for adjusting the phase variation which overlaps the delay range of the first fine delay of the first loop.
Frederick B. Jenne - Los Gatos CA, US Gary A. Gibbs - San Jose CA, US
Assignee:
Silicon Magnetic Systems - San Jose CA
International Classification:
G11C 11/00 G11C 11/14 G11C 11/15
US Classification:
365158, 365171, 365173
Abstract:
A memory array configuration is provided that includes a plurality of magnetic cell junctions and a conductive line comprising a gate of a first transistor configured to enable a read operation for one of a plurality of magnetic cell junctions and a gate of a second transistor configured to enable a write operation for another of the plurality of magnetic cell junctions. Another memory array configuration is provided which includes a set of conductive structures serially coupled to a bit line spaced apart from and, in some embodiments, directly above a magnetic cell junction, a transistor coupled to the set of conductive structures and a program line collectively configured with the bit line to induce current flow through the set of conductive structures upon an application of a voltage to a gate of the transistor. A method for operating such a magnetic memory array is also contemplated herein.
Fredrick L. Jenne - Los Gatos CA, US Gary A. Gibbs - San Jose CA, US
Assignee:
Silicon Magnetic Systems - San Jose CA
International Classification:
G11C 11/15
US Classification:
365173, 3652255, 365158, 36518905
Abstract:
A memory storage circuit is provided which includes a plurality of magnetic elements each configured to store bits in a first or a second logic state. The storage circuit may further include a plurality of transistors coupled to at least two of the magnetic elements. Such a plurality of transistors may be collectively configured to store bits in the first and second logic states as well. The memory storage circuit may include circuitry configured to load bits from a set of the magnetic elements into the plurality of transistors. Another circuit is provided which includes a magnetic element interposed between a bit line and an electrode. The circuit may further include a first set of circuitry configured to induce current flow through the magnetic element in a direction from the electrode to the bit line. A method for operating a memory storage circuit with the aforementioned configurations is also provided.
Magnetic Memory Array With An Improved World Line Configuration
Frederick B. Jenne - Los Gatos CA, US Gary A. Gibbs - San Jose CA, US
Assignee:
Silicon Magnetic Systems - San Jose CA
International Classification:
G11C 11/00
US Classification:
365158, 365145, 365171
Abstract:
A magnetic memory array with an improved word line configuration is provided. In some embodiments, the magnetic memory array may be adapted to selectively supply voltage from a single source line to one or more transistors arranged within a first row of the magnetic memory array and to one or more transistors arranged within a second row of the magnetic memory array. In addition or alternatively, the magnetic memory array may be configured to enable current flow along a single current path through a magnetic junction and along multiple paths extending from the single current path to a plurality of transistors. In some embodiments, the plurality of transistors may be formed from a contiguous conductive structure comprising the word line. In some cases, the word line may be configured to include at least two transistors that share a common diffusion region.
Steven Sanders - Belmont CA, US Gary Gibbs - San Jose CA, US Ashish Pancholy - Milpitas CA, US Gajender Rohilla - Bangalore, IN Pulkit Shah - Bangalore, IN
Assignee:
Cypress Semiconductor Corporation - San Jose CA
International Classification:
H01S 3/00
US Classification:
372 3802, 372 3801, 372 3807
Abstract:
The apparatus includes a diode laser and a current source interconnected with the diode laser. Two independent circuits in the current source are configured to limit current flowing through the diode laser. A first current limiter circuit configured to limit a current output from the current source to an anode of the diode laser, and an independent second current limiter circuit configured to limit a current return from a cathode of the diode laser to the current source so that laser output power does not exceed a specified maximum regardless of a single fault in either the first or second current limiter circuits.
Medicine Doctors
Dr. Gary R Gibbs, Salinas CA - DO (Doctor of Osteopathic Medicine)
Dec 2014 to 2000 Contact Center Consultant IIThe Bank of New York Mellon Pittsburgh, PA Jun 2011 to Nov 2014 Reconcilement Wire SpecialistPNC Financial Services Pittsburgh, PA Sep 2007 to May 2011 Financial Services ConsultantJones Lang Lasalle Pittsburgh, PA Sep 2006 to Sep 2007 Property Services SpecilistLeonard Security Services Pittsburgh, PA Nov 2003 to Sep 2006 Security Guard OfficerPrecision Response Corporation West Mifflin, PA Jun 2002 to Feb 2005 Customer Service Specialist I
Education:
Sawyer School of Business Pittsburgh, PA 1991 to 1992 Business ManagementWestern School of Business Pittsburgh, PA 1990 to 1991 Hospitality and Business ManagementComputer Tech Pittsburgh, PA 1988 to 1989 BUSINESS MANAGEMENT
split their two-game all-time series. Under head coach Barry Switzer, No. 4 OU posted a 28-10 win on Sept. 17, 1988, in Norman. The following year, under head coach Gary Gibbs, the No. 6 Sooners lost a 6-3 contest on Sept. 16 in Tucson. Coached by Dick Tomey, the Wildcats were unranked in both games.
Date: Dec 03, 2023
Category: Sports
Source: Google
Sean Payton: Too easy to single out special-teams coordinator
Unlike those high-profile defensive coordinators who have come and gone over the years (Gary Gibbs, Gregg Williams, Steve Spagnuolo, Ryan and now Dennis Allen), McMahon has operated in relative obscurity for most of his 11 years in New Orleans the first two as an assistant to John Bonamego.
Date: Nov 18, 2016
Source: Google
NFL Week 13 Picks: Brady vs. Rodgers, with a Little Help from Their Friends
The Ravens, Steelers and Browns all committed to the old Mike Shanahan-Gary Gibbs zone-stretch scheme this season: the Ravens and Browns by hiring first-generation disciples Gary Kubiak and Kyle Shanahan as coordinators, the Steelers by adding line coach Mike Munchak. A dude named Christopher Gonos
Date: Nov 29, 2014
Category: Sports
Source: Google
Drew Brees suing former teammate Kevin Houser over tax credits
The Associated Press first reported news of Brees lawsuiton Monday.The AP also reported that former Saints defensive coordinator Gary Gibbs and tight end Jeremy Shockey settled with Houser Monday.
Meanwhile, former New Orleans Saints tight end Jeremy Shockey and former Saints defensive coordinator Gary Gibbs reached separate settlements Monday with Houser over the same bogus investment deal. Terms were confidential.
Date: Jun 10, 2013
Category: Sports
Source: Google
Rob Ryan hired as Saints' defensive coordinator, Kwan is new assistant special ...
When Payton took over as head coach in 2006, New Orleans had a 4-3 scheme overseen by Gary Gibbs, who was fired after the 2008 season. In 2009, Payton brought in Gregg Williams, whose hybrid scheme used a 4-3 base alignment but switched to a 3-4 in certain situations, usually on passing downs in ord
Date: Feb 09, 2013
Source: Google
New Orleans Saints hire Rob Ryan as their new defensive coordinator
Saints Coach Sean Payton interviewed Ryan for the job on Friday in New Orleans. Ryan is the fourth defensive coordinator Payton has hired since coming to New Orleans in 2006 with the others being Gary Gibbs, Gregg Williams and Spagnuolo.
Date: Feb 09, 2013
Category: Sports
Source: Google
Belcher to Chiefs: I have hurt my girl; I can't go back
on Dec. 1 before driving to the Chiefs' practice facility and committing suicide in front of Chiefs general manager Scott Pioli, head coach Romeo Crennel and linebackers coach Gary Gibbs. Belcher was in his fourth year with the Chiefs, and had developed from an undrafted player out of the Universit