Gary Lynn Howe

US Patent:

6707722, Mar 16, 2004

Filed:

Jul 23, 2002

Appl. No.:

10/202556

Inventors:

Duc Ho - Allen TX
Gary L. Howe - Plano TX

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G11C 700

US Classification:

36518905, 36518911

Abstract:

An improved predriver circuit for an output buffer is provided that can enable the output buffer to operate well within maximum and minimum IOL current specifications at lower internally regulated voltages. The predriver circuit comprises a limiter device configured to limit or otherwise regulate the maximum gate voltage provided to the gate of the pull-down transistor device. As a result, the pull-down transistor device can be sized optimally to provide additional margin to exceed the minimum IOL specification, while also improving the margin under the maximum IOL specification. The device is configured to limit the maximum gate voltage of the output pull-down transistor device to less than the maximum external power supply voltage.

US Patent:

6826092, Nov 30, 2004

Filed:

Jan 20, 2004

Appl. No.:

10/761782

Inventors:

Duc Ho - Allen TX
Gary L. Howe - Plano TX

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G11C 700

US Classification:

36518905, 36518911

Abstract:

An improved predriver circuit for an output buffer is provided that can enable the output buffer to operate well within maximum and minimum IOL current specifications at lower internally regulated voltages. The predriver circuit comprises a limiter device configured to limit or otherwise regulate the maximum gate voltage provided to the gate of the pull-down transistor device. As a result, the pull-down transistor device can be sized optimally to provide additional margin to exceed the minimum IOL specification, while also improving the margin under the maximum IOL specification. The device is configured to limit the maximum gate voltage of the output pull-down transistor device to less than the maximum external power supply voltage.

US Patent:

6944079, Sep 13, 2005

Filed:

Dec 31, 2003

Appl. No.:

10/750736

Inventors:

Gary L. Howe - Plano TX, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G11C007/02

US Classification:

365207, 36518905

Abstract:

The present technique relates to a method and apparatus for detecting a change in a data signal at a buffer device. In the buffer device, first stage comparators may be adapted to receive a data signal and either a first voltage timing reference (VTR) signal or a complimentary VTR signal. The first stage comparators may each deliver an output signal to second stage comparators. Each of the second stage comparators receives the output signal from each of the first stage comparators. From the first stage comparator signals, the second stage comparators produce an output signal, such as a first output signal and a second output signal. These output signals from the second stage comparators are differential signals.

US Patent:

20130265834, Oct 10, 2013

Filed:

Apr 10, 2012

Appl. No.:

13/443661

Inventors:

Vijayakrishna J. Vankayala - Allen TX, US
Gary Howe - Plano TX, US
John Winegard - Plano TX, US
Vipul Surlekar - Allen TX, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G11C 7/06
G11C 7/12

US Classification:

365190, 365203, 365207, 3652101

Abstract:

Apparatuses and methods for improved memory cycle times are disclosed. An example apparatus may include first and second lines and a sense amplifier. The sense amplifier is directly coupled to the first and second lines. The sense amplifier may sense a differential signal between the first and second lines and amplify the same. An example method may include accessing a first memory cell coupled to a first line of a pair of lines and accessing a second memory cell coupled to a second line of the pair of lines. A differential is sensed between the pair of lines with a sense amplifier coupled directly to the pair of lines, and the sensed differential is amplified. The sense amplifier is coupled to an input/output bus to provide the amplified sensed differential to the input/output bus.

US Patent:

52784584, Jan 11, 1994

Filed:

Dec 13, 1991

Appl. No.:

7/807545

Inventors:

Wayland B. Holland - Garland TX
Gary L. Howe - Stafford TX
John F. Schreck - Houston TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H05K 301
H05K 5153

US Classification:

3072723

Abstract:

One aspect of the present invention includes a circuit for detecting when an input voltage exceeds a predetermined threshold. The circuit for detecting includes an input for receiving the input voltage. Further, the circuit includes a plurality of switching devices, wherein each of the switching devices comprises a first and second terminal for defining a variable conductive path, and a third terminal for receiving a signal to control said variable conductive path. The plurality of switching devices includes three switching devices. The first switching device has a first terminal coupled to the input and a second terminal coupled to a first node. The second switching device has a first terminal coupled to the first node and a second terminal coupled to a second node. Finally, the third switching device has a first terminal coupled to the second node. Each of the first, second and third switching devices are of like conductivity type, and the second node provides a first voltage if the input voltage is below the predetermined threshold and provides a second voltage if the input voltage is above the predetermined threshold.

US Patent:

20220391334, Dec 8, 2022

Filed:

Aug 6, 2022

Appl. No.:

17/882550

Inventors:

- Boise ID, US
Vaughn N. Johnson - Boise ID, US
Kyle Alexander - Boise ID, US
Gary L. Howe - Allen TX, US
Brian T. Pecha - Boise ID, US
Miles S. Wiscombe - Boise ID, US

International Classification:

G06F 13/16
G11C 11/406
G11C 11/4096

Abstract:

Memory devices and systems with improved command/address bus utilization are disclosed herein. In one embodiment, a memory device comprises a plurality of external command/address terminals and a command decoder. The plurality of external command/address terminals are configured to receive a command as a corresponding plurality of command/address bits. A first set of the command/address bits indicate a read or write operation. A second set of the command/address bits indicate whether to execute a refresh operation. The memory device is configured to, in response to the first set of command/address bits, execute the read or write operation on a portion of a memory array. The memory device is further configured to, in response to the second set of command/address bits, execute the refresh operation to refresh at least one memory bank of the memory array when the second set of command/address bits indicate that the refresh operation should be executed.

US Patent:

20220375507, Nov 24, 2022

Filed:

Aug 4, 2022

Appl. No.:

17/881482

Inventors:

- Boise ID, US
Scott E. Smith - Plano TX, US
Gary L. Howe - Allen TX, US
Brian W. Huber - Allen TX, US
Tony M. Brewer - Plano TX, US

International Classification:

G11C 11/408
G11C 11/4096
G11C 11/406

Abstract:

Memory devices, systems including memory devices, and methods of operating memory devices are described, in which memory devices are configured to provide row clear features. In some embodiments, the memory device may receive a command from a host device directed to a row of a memory array included in the memory device. The memory device may determine that the command is directed to two or more columns associated with the row, where each column is coupled with a group of memory cells. The memory device may activate the row to write the two or more columns using a set of predetermined data stored in a register of the memory device. Subsequently, the memory device may deactivate the word line based on writing the set of predetermined data to the two or more columns.

US Patent:

20220262413, Aug 18, 2022

Filed:

Feb 18, 2021

Appl. No.:

17/178475

Inventors:

- Boise ID, US
Gary L. Howe - Allen TX, US

International Classification:

G11C 7/10
G11C 11/4076
G11C 11/4093

Abstract:

Systems and methods described herein provide decision feedback equalizer (DFE) circuitry that includes one or more phases. The one or more phases receive bit feedback at respective inputs of the phases. The DFE circuitry also may include variable reset circuitry. The variable reset circuitry may reset voltages of the bit feedback at inputs of each of the phases. The variable reset circuitry is configured to change its reset frequency between resets.