Gary M Howe

US Patent:

20220391334, Dec 8, 2022

Filed:

Aug 6, 2022

Appl. No.:

17/882550

Inventors:

- Boise ID, US
Vaughn N. Johnson - Boise ID, US
Kyle Alexander - Boise ID, US
Gary L. Howe - Allen TX, US
Brian T. Pecha - Boise ID, US
Miles S. Wiscombe - Boise ID, US

International Classification:

G06F 13/16
G11C 11/406
G11C 11/4096

Abstract:

Memory devices and systems with improved command/address bus utilization are disclosed herein. In one embodiment, a memory device comprises a plurality of external command/address terminals and a command decoder. The plurality of external command/address terminals are configured to receive a command as a corresponding plurality of command/address bits. A first set of the command/address bits indicate a read or write operation. A second set of the command/address bits indicate whether to execute a refresh operation. The memory device is configured to, in response to the first set of command/address bits, execute the read or write operation on a portion of a memory array. The memory device is further configured to, in response to the second set of command/address bits, execute the refresh operation to refresh at least one memory bank of the memory array when the second set of command/address bits indicate that the refresh operation should be executed.

US Patent:

20230096291, Mar 30, 2023

Filed:

Sep 29, 2021

Appl. No.:

17/449297

Inventors:

- BOISE ID, US
Scott Smith - Boise ID, US
Christian Mohr - Boise ID, US
Gary Howe - Boise ID, US
Joshua Alzheimer - Boise ID, US
Yoshinori Fujiwara - Boise ID, US
Sujeet Ayyapureddi - Boise ID, US
Randall Rooney - Boise ID, US

Assignee:

MICRON TECHNOLOGY, INC. - BOISE ID

International Classification:

G11C 29/44
G11C 29/18
G11C 29/46
G11C 29/00

Abstract:

Embodiments of the disclosure are drawn to apparatuses and methods for bad row mode. The memory may prevent proper access operations (e.g., read operations) from being performed on a selected bad row of the memory as part of a bad row mode. For example, the memory may store a bad row address and when an access address matches the bad row address, may suppress one or more signals, change data read from the address, or combinations thereof. The bad row mode may be used to provide a positive control for post package repair (PPR) operations on the memory. A controller may enter the memory into bad row mode and then test the memory to determine if the selected bad row can be located and repaired via PPR.