Gary Lin

US Patent:

8060849, Nov 15, 2011

Filed:

Feb 26, 2008

Appl. No.:

12/037453

Inventors:

Yanyan He - Cupertino CA, US
Gary Lin - Cupertino CA, US
Hung Nguyen - San Jose CA, US
MingFu Gong - Fremont CA, US

Assignee:

Mentor Graphics Corporation - Wilsonville OR

International Classification:

G06F 17/50

US Classification:

716126, 716111, 716112, 716130, 716137, 716139

Abstract:

Particular embodiments generally relate to automatic routing of a bus in an integrated circuit design. In one embodiment, a method includes receiving a description of a circuit design. Buses are automatically detected based on pin adjacency in terms of distance between pins and routing layer of the pins. A bus routing area is determined by the bounding box of first group of source pins and a second group of destination pins. Bus routing guidance is then generated by an automatically search engine in the bus routing area. The bus routing guidance models a bus as a skinny wire with large spacing, and it does not violate design rules. Real bus wires are generated based on the bus guidance. A bus is then automatically routed between a first group of source pins and a second group of destination pins based on the bus routing guidance.

US Patent:

8443263, May 14, 2013

Filed:

Dec 30, 2009

Appl. No.:

12/650263

Inventors:

Robert D. Selinger - San Jose CA, US
Gary Lin - San Jose CA, US
Paul Lassa - Cupertino CA, US
Chaoyang Wang - Cupertino CA, US

Assignee:

SanDisk Technologies Inc. - Plano TX

International Classification:

G06F 11/00

US Classification:

714768

Abstract:

The embodiments described herein provide a method and controller for performing a copy-back command. In one embodiment, a controller receives the data and error correction code associated with a copy-back operation from at least one flash memory device. The controller determines if the error correction code indicates there is an error in the data. If the error correction code does not indicate there is an error in the data, the controller sends a destination address and copy-back program command received from a host to the at least one flash memory device. If the error correction code indicates there is an error in the data, the controller corrects the data and sends the destination address, the corrected data, and a program command to the at least one flash memory device. Additional embodiments relate to modifying data during the copy-back operation.

US Patent:

8595411, Nov 26, 2013

Filed:

Dec 30, 2009

Appl. No.:

12/650255

Inventors:

Robert D. Selinger - San Jose CA, US
Gary Lin - San Jose CA, US
Chaoyang Wang - Cupertino CA, US

Assignee:

SanDisk Technologies Inc. - Plano TX

International Classification:

G06F 13/00

US Classification:

711103

Abstract:

The embodiments described herein provide a method and controller for performing a sequence of commands. In one embodiment, a controller receives a command from a host to perform a memory operation in a flash memory device, wherein the command comprises at least one bit that indicates whether the command is a stand-alone command or is part of a sequence of commands. The controller analyzes the at least one bit to determine whether the at least one bit indicates that the command is a stand-alone command or is part of a sequence of commands. If the at least one bit indicates that the command is a stand-alone command, the controller performs the command. If the at least one bit indicates that the command is part of a sequence of commands, the controller performs the command as part of the sequence of commands.

US Patent:

20120331282, Dec 27, 2012

Filed:

Nov 15, 2011

Appl. No.:

13/296898

Inventors:

Damian P. Yurzola - Santa Clara CA, US
Rajeev Nagabhirava - Santa Clara CA, US
Gary J. Lin - San Jose CA, US
Matthew Davidson - Mountain View CA, US
Paul A. Lassa - Cupertino CA, US

Assignee:

SANDISK TECHNOLOGIES, INC. - Milpitas CA

International Classification:

G06F 9/00

US Classification:

713100

Abstract:

Disclosed are apparatus and techniques for managing power in a memory system having a controller and nonvolatile memory array. In one embodiment, prior to execution of each command with respect to the memory array, a request for execution of such command is received with respect to the memory array. In response to receipt of each request for each command, execution of such command is allowed or withheld with respect to the memory array based on whether such command, together with execution of other commands, is estimated to exceed a predetermined power usage specification for the memory system.

US Patent:

20130262745, Oct 3, 2013

Filed:

Mar 30, 2012

Appl. No.:

13/436313

Inventors:

Gary Lin - San Jose CA, US
Matthew Davidson - Mountain View CA, US

International Classification:

G06F 12/00

US Classification:

711103, 711E12008

Abstract:

A non-volatile memory system includes a memory controller that receives commands from a host and identifies commands that can be executed in parallel. The order in which commands are received is recorded so that responses may be provided to the host in the same order in which the commands were received.

US Patent:

53961650, Mar 7, 1995

Filed:

Feb 2, 1993

Appl. No.:

8/013809

Inventors:

Jeffrey H. Hwang - Saratoga CA
Peter Reischl - Los Gatos CA
Wen H. Yu - San Francisco CA
Kartik Bhatt - Newark CA
Gary J. Lin - Campbell CA
George C. Chen - Milpitas CA

Assignee:

Teledyne Industries, Inc. - Mountain View CA

International Classification:

G05F 170

US Classification:

323210

Abstract:

A power transfer method and apparatus for efficient transfer of power are disclosed. Input power is converted in an essentially lossless manner to an intermediate form having a voltage or current in excess of that desired at the load. The intermediate power form is split into first and second parts, where the first part of the intermediate power form approximately matches an output power form desired at an output of the power transfer apparatus and the second part represents an excess power form. The first part of the intermediate power form is transferred to the output of the power transfer apparatus and the excess part is stored. Part or all of the stored excess energy is recycled in an essentially lossless manner, converted into a form that approximately matches the output power form desired at the output of the power transfer apparatus and transferred to the output of the power transfer apparatus.

US Patent:

20170160931, Jun 8, 2017

Filed:

Jun 7, 2016

Appl. No.:

15/176070

Inventors:

- Plano TX, US
Gary Lin - San Jose CA, US
Robert Gugel - Longmont CO, US

International Classification:

G06F 3/06

Abstract:

The various implementations described herein include systems, methods and/or devices for storing data in a storage device. In one aspect, commands are executed, each command for storing in a storage device a logical group of data comprising one or more logical portions and having a logical address. For each command, in accordance with a determination that a remaining capacity of a first physical memory portion is less than a threshold capacity, data is stored for a head logical portion in a first physical location corresponding to the first physical memory portion. Furthermore, data is stored for a tail logical portion in a second physical location corresponding to a second physical memory portion. Mapping entries are stored in a mapping table, where the mapping entries map the corresponding logical address to at least the first physical location in the storage device.

US Patent:

20170160932, Jun 8, 2017

Filed:

Jun 7, 2016

Appl. No.:

15/176074

Inventors:

- Plano TX, US
Gary Lin - San Jose CA, US
Robert Gugel - Longmont CO, US

International Classification:

G06F 3/06

Abstract:

The various implementations described herein include systems, methods and/or devices for reading data stored in a storage device. In one aspect, read commands are executed, each command for reading a requested logical group of data from a specified logical address comprising one or more logical portions. A first physical location in the storage device corresponding to the logical address is identified from a mapping table, and data is read. In accordance with a determination that the first physical location stores less than all of the logical group of data, a second physical location is identified based on information contained within the data from the first physical location, and data is read from the second physical location. Data read from the one or more physical locations is decoded to produce the requested logical group of data, which is then returned.