Gary Paul Lucas

US Patent:

7058793, Jun 6, 2006

Filed:

Dec 20, 1999

Appl. No.:

09/468051

Inventors:

Thomas D. Hartnett - Roseville MN, US
John S. Kuslak - Blaine MN, US
Gary J. Lucas - Pine Springs MN, US

Assignee:

Unisys Corporation - Blue Bell PA

International Classification:

G06F 9/40

US Classification:

712219

Abstract:

A synchronous pipeline design is provided that includes a first predetermined number of fetch logic sections, or “stages”, and a second predetermined number of execution stages. Instructions are retrieved from memory and undergo instruction pre-decode and decode operations during the fetch stages of the pipeline. Thereafter, decoded instruction signals are passed to the execution stages of the pipeline, where the signals are dispatched to other execution logic sections to control operand address generation, operand retrieval, any arithmetic processing, and the storing of any generated results. Instructions advance within the various pipeline fetch stages in a manner that may be independent from the way instructions advance within the execution stages. Thus, in certain instances, instruction execution may stall such that the execution stages of the pipeline are not receiving additional instructions to process. This may occur, for example, because an operand required for instruction execution is unavailable.

US Patent:

7114063, Sep 26, 2006

Filed:

Dec 1, 2000

Appl. No.:

09/727744

Inventors:

Lawrence Richard Fontaine - Minneapolis MN, US
John Steven Kuslak - Blaine MN, US
Gary John Lucas - Pine Springs MN, US
Michael David Pelarski - Fridley MN, US

Assignee:

Unisys Corporation - Blue Bell PA

International Classification:

G06F 9/44

US Classification:

712235

Abstract:

A branch prediction method and system are provided that accurately predict a branch condition early in an instruction pipeline of a data processing system. By accurately predicting the branch condition, the correct target instruction can be fetched early, thereby avoiding many of the inefficiencies associated with branch mispredictions. To accurately predict if a branch condition is satisfied, one or more pre-calculated status bits are stored along with a digital value that is read by the conditional branch instruction to determine if the branch condition is satisfied. By including such a status bit, the condition of the conditional branch instruction may be immediately determined, without waiting for the instruction to be processed by an arithmetic unit or the like in a subsequent pipeline stage.

US Patent:

7827455, Nov 2, 2010

Filed:

May 1, 2007

Appl. No.:

11/799304

Inventors:

Nathan A. Eckel - Fridley MN, US
Peter Levinshteyn - Blaine MN, US
Gary J. Lucas - Pine Springs MN, US

Assignee:

Unisys Corporation - Blue Bell PA

International Classification:

G11C 29/00
G11B 5/00
G11B 20/20
G06K 5/04
G01R 31/26

US Classification:

714735, 714700, 714712, 714724, 365201, 324765

Abstract:

The current invention provides a mechanism for detecting and recovering from glitches on data strobes. In one embodiment, data is captured from an interlace by a receiver using at least one data strobe that is provided by the transmitter along with the data. A write address counter that is clocked by the data strobe is used to count the active edges of the data strobe. A read address counter that is periodically synchronized with the write address counter, but that is clocked by an internal clock of the receiver, is used to count units of data being received from the interface. Periodically, the contents of the read and write counters are compared. If the contents are not the same, a glitch has occurred on the data strobe. The glitch is recoverable if it occurs on, or after, a last strobe edge of a data transfer.

US Patent:

20100162269, Jun 24, 2010

Filed:

Dec 22, 2008

Appl. No.:

12/340838

Inventors:

Gary J. Lucas - Pine Springs MN, US
Paul S. Neuman - Shoreview MN, US

International Classification:

G06F 9/44

US Classification:

719318

Abstract:

An apparatus and method are provided for describing the interaction between event monitoring subsystems. A plurality of interactively-connected event monitoring subsystems in a computing system are configured. Events are collected by a first event monitoring subsystem of the plurality of event monitoring subsystems. Additional event information regarding one or more additional events are collected by the one or more second event monitoring systems. This additional information is received at the first event monitoring subsystem from one or more second event monitoring subsystems. An action is also triggered by the first event monitoring subsystem. The action is based on one or both of the collected performance events and the additional performance event information.

US Patent:

58729100, Feb 16, 1999

Filed:

Dec 27, 1996

Appl. No.:

8/777221

Inventors:

John Steven Kuslak - Blaine MN
Gary John Lucas - Pine Springs MN
Nguyen Thai Tran - Mountain View CA

Assignee:

Unisys Corporation - Blue Bell PA

International Classification:

G06F 1100

US Classification:

39518317

Abstract:

A system and method for selectively injecting parity errors into instructions after the instructions are fetched from a storage device and are resident within the instruction processor in a data processing system. The parity errors are selectively injected according to programmable indicators, each programmable indicator being associated with one or more instructions stored in the storage device. The error-injection system also includes programmable operating modes whereby error injection will occur after every fetch of an associated instruction, or alternatively, after alternate fetches of an associated instruction. The system allows for comprehensive testing of error detection and recovery logic in an instruction processor, and further allows for comprehensive testing of the logic associated with performing a data re-fetch from the storage device.

US Patent:

57245339, Mar 3, 1998

Filed:

Nov 17, 1995

Appl. No.:

8/558246

Inventors:

John S. Kuslak - Blaine MN
Gary J. Lucas - Pine Springs MN

Assignee:

Unisys Corporation - Blue Bell PA

International Classification:

G06F 9312

US Classification:

395381

Abstract:

A method of and apparatus for efficiently halting the operation of the instruction processor when a cache miss is detected. Generally, this is accomplished by preventing unwanted address incrementation of an instruction address pipeline and by providing a null instruction to an instruction pipeline when a cache miss is detected. Accordingly, the present invention may eliminate a recovery period after a cache miss, thereby enhance the performance of the data processing system. Further, the present invention may eliminate recovery hardware required to support the recovery process.

US Patent:

58676996, Feb 2, 1999

Filed:

Jul 25, 1996

Appl. No.:

8/686258

Inventors:

John S. Kuslak - Blaine MN
David C. Johnson - Roseville MN
Gary J. Lucas - Pine Springs MN
Kenneth L. Engelbrecht - Blaine MN

Assignee:

Unisys Corporation - Blue Bell PA

International Classification:

G06F 938
G06F 930

US Classification:

395587

Abstract:

Method and apparatus for changing the sequential execution of instructions in a pipelined instruction processor by using a microcode controlled redirect controller. The execution of a redirect instruction by the pipelined instruction processor provides a number of microcode bits including a target address to the redirect controller, a predetermined combination of the microcode bits then causes the redirect controller to redirect the execution sequence of the instructions from the next sequential instruction to a target instruction.

US Patent:

56447590, Jul 1, 1997

Filed:

Jan 19, 1995

Appl. No.:

8/375219

Inventors:

Gary J. Lucas - Pine Springs MN
Ronald G. Arnold - Apple Valley MN

Assignee:

Unisys Corporation - Blue Bell PA

International Classification:

G06F 942

US Classification:

395587

Abstract:

Disclosed is a system for improved instruction fetch prediction. When a jump instruction is encountered, the preceding instruction is considered in predicting the next instruction to fetch. If the preceding instruction is a skip instruction, the result of evaluating a condition specified by the skip instruction is used in predicting the next instruction to fetch. Prediction designators for skip/jump sequences of instructions are maintained in a jump prediction RAM.