Gary Allen Lucas

age ~73

from Claremont, CA

Also known as:
  • Gary A Lucas
  • Gary L Lucas
  • Allen G Lucas
  • Gary Lucas Allen
  • Lucas Gary Allen
  • Garyallen Lucas
  • Gary A Ucas
  • Allen Lucas Gary
Phone and address:
545 Indian Hill Blvd, Claremont, CA 91711
9096241862

Gary Lucas Phones & Addresses

  • 545 Indian Hill Blvd, Claremont, CA 91711 • 9096241862
  • Covina, CA
  • Los Angeles, CA
  • Somerset, WI
  • Poway, CA
  • 727 Lander Cir, Claremont, CA 91711 • 9096241862

Work

  • Position:
    Clerical/White Collar

Education

  • Degree:
    High school graduate or higher

Specialities

Alternative Dispute Resolution • Labor and Employment
Name / Title
Company / Classification
Phones & Addresses
Mr. Gary Lucas
President
Sapiens Insuretech, Inc.
InsureTech Alternatives. Inc.
Computers-Sys Designers & Consult. Computers Software & Services
1122 Lady Street, Suite 1145, Columbia, SC 29201
8032526511, 8032526133
Gary S Lucas
CRAZY SQUIRREL, LLC
Gary Lucas
WEST MAIN STREET CHURCH OF CHRIST
Gary Lucas
JOHN LAING (USA) LIMITED
Gary Lucas
Manager
Winroc Corporation (Midwest)
Whol Brick/Stone Matrls Whol Lumber/Plywd/Millwk
5262 Glenbrook Ave N, Saint Paul, MN 55128
6517778222
Gary Lucas
President
INSURETECH ALTERNATIVES, INC
Gary M. Lucas
EZ CREATE IMA, INC
Gary Lucas
President
FAMILIES OF INJURED VETERANS OF AMERICA
2025 Chicago Ave, Riverside, CA 92507

Wikipedia

Jeff Buckley

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…as a springboard to his career, instead citing personal reasons regarding his decision to sing at the tribute.[42] With accompaniment by experimental rock guitarist Gary Lucas, Buckley performed "I Never Asked To Be Your Mountain", a song Tim Buckley wrote about an infant Jeff Buckley and hi...

Albert Ayler

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…n Sept. 20, 1996, the first Albert Ayler Festival was held at the Washington Square Church in Greenwich Village, NY. Performing that day were Gary Lucas, Amiri Baraka, Joe McPhee Quartet, Peter Brotzman- Thomas Borgmann Quartet, Joe Giardullo Quartet, Sunny Murray, Joseph Jarman, and Thursto...

Lawyers & Attorneys

Gary Lucas Photo 1

Gary Lucas - Lawyer

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Specialties:
Alternative Dispute Resolution
Labor and Employment
ISLN:
905332701
Admitted:
1969
University:
St. Louis University, B.S.
Law School:
St. Louis University, J.D.

Us Patents

  • Pipeline Controller For Providing Independent Execution Between The Preliminary And Advanced Stages Of A Synchronous Pipeline

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  • US Patent:
    7058793, Jun 6, 2006
  • Filed:
    Dec 20, 1999
  • Appl. No.:
    09/468051
  • Inventors:
    Thomas D. Hartnett - Roseville MN, US
    John S. Kuslak - Blaine MN, US
    Gary J. Lucas - Pine Springs MN, US
  • Assignee:
    Unisys Corporation - Blue Bell PA
  • International Classification:
    G06F 9/40
  • US Classification:
    712219
  • Abstract:
    A synchronous pipeline design is provided that includes a first predetermined number of fetch logic sections, or “stages”, and a second predetermined number of execution stages. Instructions are retrieved from memory and undergo instruction pre-decode and decode operations during the fetch stages of the pipeline. Thereafter, decoded instruction signals are passed to the execution stages of the pipeline, where the signals are dispatched to other execution logic sections to control operand address generation, operand retrieval, any arithmetic processing, and the storing of any generated results. Instructions advance within the various pipeline fetch stages in a manner that may be independent from the way instructions advance within the execution stages. Thus, in certain instances, instruction execution may stall such that the execution stages of the pipeline are not receiving additional instructions to process. This may occur, for example, because an operand required for instruction execution is unavailable.
  • Controllable Interaction Between Multiple Event Monitoring Subsystems For Computing Environments

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  • US Patent:
    20100162269, Jun 24, 2010
  • Filed:
    Dec 22, 2008
  • Appl. No.:
    12/340838
  • Inventors:
    Gary J. Lucas - Pine Springs MN, US
    Paul S. Neuman - Shoreview MN, US
  • International Classification:
    G06F 9/44
  • US Classification:
    719318
  • Abstract:
    An apparatus and method are provided for describing the interaction between event monitoring subsystems. A plurality of interactively-connected event monitoring subsystems in a computing system are configured. Events are collected by a first event monitoring subsystem of the plurality of event monitoring subsystems. Additional event information regarding one or more additional events are collected by the one or more second event monitoring systems. This additional information is received at the first event monitoring subsystem from one or more second event monitoring subsystems. An action is also triggered by the first event monitoring subsystem. The action is based on one or both of the collected performance events and the additional performance event information.
  • Parity-Error Injection System For An Instruction Processor

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  • US Patent:
    58729100, Feb 16, 1999
  • Filed:
    Dec 27, 1996
  • Appl. No.:
    8/777221
  • Inventors:
    John Steven Kuslak - Blaine MN
    Gary John Lucas - Pine Springs MN
    Nguyen Thai Tran - Mountain View CA
  • Assignee:
    Unisys Corporation - Blue Bell PA
  • International Classification:
    G06F 1100
  • US Classification:
    39518317
  • Abstract:
    A system and method for selectively injecting parity errors into instructions after the instructions are fetched from a storage device and are resident within the instruction processor in a data processing system. The parity errors are selectively injected according to programmable indicators, each programmable indicator being associated with one or more instructions stored in the storage device. The error-injection system also includes programmable operating modes whereby error injection will occur after every fetch of an associated instruction, or alternatively, after alternate fetches of an associated instruction. The system allows for comprehensive testing of error detection and recovery logic in an instruction processor, and further allows for comprehensive testing of the logic associated with performing a data re-fetch from the storage device.
  • High Performance Instruction Data Path

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  • US Patent:
    57245339, Mar 3, 1998
  • Filed:
    Nov 17, 1995
  • Appl. No.:
    8/558246
  • Inventors:
    John S. Kuslak - Blaine MN
    Gary J. Lucas - Pine Springs MN
  • Assignee:
    Unisys Corporation - Blue Bell PA
  • International Classification:
    G06F 9312
  • US Classification:
    395381
  • Abstract:
    A method of and apparatus for efficiently halting the operation of the instruction processor when a cache miss is detected. Generally, this is accomplished by preventing unwanted address incrementation of an instruction address pipeline and by providing a null instruction to an instruction pipeline when a cache miss is detected. Accordingly, the present invention may eliminate a recovery period after a cache miss, thereby enhance the performance of the data processing system. Further, the present invention may eliminate recovery hardware required to support the recovery process.
  • Instruction Flow Control For An Instruction Processor

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  • US Patent:
    58676996, Feb 2, 1999
  • Filed:
    Jul 25, 1996
  • Appl. No.:
    8/686258
  • Inventors:
    John S. Kuslak - Blaine MN
    David C. Johnson - Roseville MN
    Gary J. Lucas - Pine Springs MN
    Kenneth L. Engelbrecht - Blaine MN
  • Assignee:
    Unisys Corporation - Blue Bell PA
  • International Classification:
    G06F 938
    G06F 930
  • US Classification:
    395587
  • Abstract:
    Method and apparatus for changing the sequential execution of instructions in a pipelined instruction processor by using a microcode controlled redirect controller. The execution of a redirect instruction by the pipelined instruction processor provides a number of microcode bits including a target address to the redirect controller, a predetermined combination of the microcode bits then causes the redirect controller to redirect the execution sequence of the instructions from the next sequential instruction to a target instruction.
  • Apparatus And Method For Processing A Jump Instruction Preceded By A Skip Instruction

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  • US Patent:
    56447590, Jul 1, 1997
  • Filed:
    Jan 19, 1995
  • Appl. No.:
    8/375219
  • Inventors:
    Gary J. Lucas - Pine Springs MN
    Ronald G. Arnold - Apple Valley MN
  • Assignee:
    Unisys Corporation - Blue Bell PA
  • International Classification:
    G06F 942
  • US Classification:
    395587
  • Abstract:
    Disclosed is a system for improved instruction fetch prediction. When a jump instruction is encountered, the preceding instruction is considered in predicting the next instruction to fetch. If the preceding instruction is a skip instruction, the result of evaluating a condition specified by the skip instruction is used in predicting the next instruction to fetch. Prediction designators for skip/jump sequences of instructions are maintained in a jump prediction RAM.
  • Method Of And Apparatus For Saving Time Performing Certain Transfer Instructions

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  • US Patent:
    61087610, Aug 22, 2000
  • Filed:
    Feb 20, 1998
  • Appl. No.:
    9/026840
  • Inventors:
    David C. Johnson - Roseville MN
    John S. Kuslak - Blaine MN
    Gary J. Lucas - Pine Springs MN
  • Assignee:
    Unisys Corporation - Blue Bell PA
  • International Classification:
    G06F 1200
  • US Classification:
    711214
  • Abstract:
    A method and apparatus for reducing processor response time to selected transfer instructions in an multi-instruction processor. The response time is shortened by using a fast path to generate addresses for selected transfer instructions. In this fast path a base address, retained in a register from a previous instruction, is summed with an offset from the current instruction to obtain an absolute address for memory accessing. Before the fast path is entered determinations are made whether the instruction is a particular transfer instruction of a particular class and subclass, and whether the base address is different than the base address for the previous instruction. Even through the fast path is entered the usual absolute address generator path is also entered where the instruction is subjected to both high and low limit tests. If the high and low limit test determine a different base is to be used, the absolute address from the main address generator is used, instead of the absolute address from the LXJ fast path, and the system is restored to the conditions that would have prevailed if the fast path had not been entered.
  • Method Of And Apparatus For Speeding Up The Execution Of Normal Extended Mode Transfer Instructions

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  • US Patent:
    60818816, Jun 27, 2000
  • Filed:
    Feb 20, 1998
  • Appl. No.:
    9/026935
  • Inventors:
    David C. Johnson - Roseville MN
    Gary J. Lucas - Pine Springs MN
  • Assignee:
    Unisys Corporation - Blue Bell PA
  • International Classification:
    G06F 1200
  • US Classification:
    711220
  • Abstract:
    A method and apparatus for reducing processor response time to selected transfer instructions in an instruction processor using a plurality of memory banks including four banks in a basic mode and one memory bank in an extended mode. This invention provides fast transfer hardware to improve the response time by a speed up transfer for normal extended mode transfer instructions only. The bank descriptor of the instruction is used to determine appropriate transfer instructions which are then tested for characteristics indicating whether a fast transfer is possible. The fast transfer process requires fewer checks than the previous apparatus which accelerates the response to selected transfer instructions by one cycle.

License Records

Gary Lucas

License #:
C000334 - Expired
Category:
Social Work
Issued Date:
Jul 1, 1990
Expiration Date:
Jun 30, 2009 - Non-acticingpr
Type:
Clinical Social Worker

Gary K Lucas

License #:
E064194 - Expired
Category:
Emergency medical services
Issued Date:
Feb 10, 2008
Expiration Date:
Oct 31, 2012
Type:
Marin County EMS Agency

Plaxo

Gary Lucas Photo 2

Gary Mark Lucas

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Boston, MAData Tape Operator at Sun Life Financial / IBM
Gary Lucas Photo 3

Gary Lucas

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Gary Lucas Photo 4

Gary Lucas

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C Robert Wynn Associates
Gary Lucas Photo 5

Gary Lucas

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Project Engineer at Dynatec

Googleplus

Gary Lucas Photo 6

Gary Lucas

Work:
Living by the lays of theTao - Student (1972)
Communications N.O.W. - Owner (1992)
US Navy - Ship Fitter 3rd Class (1963-1968)
Life
Education:
Hard Knocks - Surviving comfortably
Tagline:
Helping People Help Them Selves Through Neutral Awareness
Gary Lucas Photo 7

Gary Lucas

Education:
TulsaWill rogers
Gary Lucas Photo 8

Gary Lucas

Tagline:
A lone man in search of Superwoman.
Bragging Rights:
Im still here.
Gary Lucas Photo 9

Gary Lucas

Gary Lucas Photo 10

Gary Lucas

Gary Lucas Photo 11

Gary Lucas

Gary Lucas Photo 12

Gary Lucas

Gary Lucas Photo 13

Gary Lucas

Youtube

GO GO GOLEM: Gary Lucas plays "The Golem" liv...

Thanks to John Beckmann for the clip. For more info on Gary Lucas's li...

  • Duration:
    22s

Jeff Buckley & Gary Lucas | CBGB | New York |...

I do not own the rights to this video. All rights belong to their resp...

  • Duration:
    32m 48s

Jeff Buckley & Gary Lucas | Knitting Factory ...

I do not own the rights to this video. All rights belong to their resp...

  • Duration:
    19m 25s

Swamp T'ing--Gary Lucas & Gods and Monsters

directed by Jill A. Black from the album "The Ordeal of Civility", pro...

  • Duration:
    4m 27s

Jeff Buckley & Gary Lucas | Roulette Club | N...

I do not own the rights to this video. All rights belong to their resp...

  • Duration:
    53m 5s

Gary Lucas TRIBUTE TO PHAROAH SANDERS 9/24/22

Here as part of his regular live stream series live from his apartment...

  • Duration:
    31m 8s

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