Gary T Lucas

US Patent:

20090164689, Jun 25, 2009

Filed:

Dec 21, 2007

Appl. No.:

12/004659

Inventors:

Mark D. Luba - Plymouth Meeting PA, US
Gary J. Lucas - Pine Springs MN, US
Kelvin S. Vartti - Hugo MN, US

International Classification:

G06F 12/00
G06F 13/16

US Classification:

710305, 711167, 711E12001

Abstract:

A data processing system is described that reduces read latency of requested memory data, thereby resulting in improved system performance. An exemplary system includes a bus, a processor, and a controller associated with the processor. The controller is configured to send a request for data to a memory storage unit, receive, from the memory storage unit, an early response indicating that the controller will later receive the requested data, and upon receipt of the early response indicator, start a timer to wait a period of time. The controller is further configured to, after expiration of the timer but prior to receipt of the requested data, send an arbitration request to initiate a transaction on the bus to communicate the requested data from the controller to the processor when the requested data is later received by the controller.

US Patent:

20100131719, May 27, 2010

Filed:

Jan 27, 2010

Appl. No.:

12/694652

Inventors:

Mark D. Luba - Plymouth Meeting PA, US
Gary J. Lucas - Pine Springs MN, US
Kelvin S. Vartti - Hugo MN, US

International Classification:

G06F 12/00
G06F 12/08
G06F 13/36

US Classification:

711146, 710113, 711E12001, 711E12033

Abstract:

A data processing system is described that reduces read latency of requested memory data, thereby resulting in improved system performance. An exemplary system includes a bus, a processor, and a controller associated with the processor. The controller is configured to send a request for data to a memory storage unit, receive, from the memory storage unit, an early response indicating that the controller will later receive the requested data, and upon receipt of the early response indicator, start a timer to wait a period of time. The controller is further configured to, after expiration of the timer but prior to receipt of the requested data, send an arbitration request to initiate a transaction on the bus to communicate the requested data from the controller to the processor when the requested data is later received by the controller.