Gary Evan Morrison

US Patent:

6762498, Jul 13, 2004

Filed:

Jul 1, 2003

Appl. No.:

10/611697

Inventors:

Gary P. Morrison - Garland TX
Gregory E. Howard - Dallas TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 2352

US Classification:

257758, 257759, 438622, 438623

Abstract:

A substrate ( ) for use in semiconductor devices, having first ( ) and second ( ) surfaces and a base structure including insulating material. A plurality of I/O terminal pads ( ) is distributed on the first and second surfaces, respectively, and these terminal pads are interconnected by conducting traces integral to the base structure. A plurality of selected metal layers ( to ) is distributed in the structure; the metal layers are substantially parallel to the surfaces and separated by the insulating material from each other and from the surfaces. At least one metal layer ( or , respectively) opposite each of the surfaces has openings ( ) therein configured so that the metal areas ( ) directly opposite each of the terminal pads ( ) are electrically isolated from the remainder of the layer. The width of these openings is selected to provide a pre-determined capacitance between each of the terminals ( ) and the remainder of the metal layer ( ).

US Patent:

7462783, Dec 9, 2008

Filed:

Aug 2, 2004

Appl. No.:

10/910506

Inventors:

Gregory E. Howard - Dallas TX, US
Navin Kalidas - Houston TX, US
Paul J. Hundt - Garland TX, US
Gary P. Morrison - Garland TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H05K 1/16

US Classification:

174260, 174262

Abstract:

Semiconductor chip () of a ball grid array device () is mounted onto tape substrate () using attach adhesive (). The metal layer on the top surface of substrate () uses between about 30% to 90% of its area for connecting lines (), and only the remainder for members/rings () and terminals (). Routing of differential pair signals and large numbers of signals on a single layer tape package are feasible. This embodiment creates an inexpensive high performance tape ball grid array package for chip-scale devices. Terminals () serve the connection (by bonding wires or reflow bumps) to the chip contact pads. Inserted in members/rings () are the conductive pins (), which serve as anchors for the solder bodies/balls (). Pins () are substantially insensitive to the thermomechanical stresses, which occur in device () during assembly, testing and operation.

US Patent:

8154134, Apr 10, 2012

Filed:

May 8, 2009

Appl. No.:

12/463184

Inventors:

Thomas D. Bonifield - Dallas TX, US
Gary P. Morrison - Garland TX, US
Rajiv Dunne - Murphy TX, US
Satyendra S. Chauhan - Sugarland TX, US
Masood Murtuza - Sugarland TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 23/48
H01L 23/52
H01L 29/40
H01L 23/495
H01L 23/04

US Classification:

257774, 257676, 257697, 257698, 257E23011, 257E23067

Abstract:

A packaged electronic device includes a leadframe including a die pad, a first, second, and third lead pin surrounding the die pad. An IC die is assembled in a face-up configuration on the lead frame. The IC die includes a substrate having an active top surface and a bottom surface, wherein the top surface includes integrated circuitry including an input pad, an output pad, a power supply pad, and a ground pad, and a plurality of through-substrate vias (TSVs) including an electrically conductive filler material and a dielectric liner. The TSVs couple the input pad to the first lead pin, the output pad to the second lead pin, the power supply pad to a third lead pin or a portion of the die pad. A fourth TSV couples pads coupled to the ground node to the die pad or a portion of the die pad for a split die pad.

US Patent:

8178976, May 15, 2012

Filed:

May 8, 2009

Appl. No.:

12/463086

Inventors:

Rajiv Dunne - Murphy TX, US
Gary P. Morrison - Garland TX, US
Satyendra S. Chauhan - Dallas TX, US
Masood Murtuza - Sugarland TX, US
Thomas D. Bonifield - Dallas TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 23/48

US Classification:

257774, 257E23174

Abstract:

A semiconductor device includes an integrated circuit (IC) die including a substrate, and at least one through substrate via (TSV) that extends through the substrate to a protruding integral tip that includes sidewalls and a distal end. The protruding integral tip has a tip height between 1 and 50 μm. A metal layer is on the bottom surface of the IC die, and the sidewalls and the distal end of the protruding integral tips. A semiconductor device can include an IC die that includes TSVs and a package substrate such as a lead-frame, where the IC die includes a metal layer and an electrically conductive die attach adhesive layer, such as a solder filled polymer wherein the solder is arranged in an electrically interconnected network, between the metal layer and the die pad of the lead-frame.

US Patent:

8431481, Apr 30, 2013

Filed:

Apr 11, 2012

Appl. No.:

13/444545

Inventors:

Rajiv Dunne - Murphy TX, US
Gary P. Morrison - Garland TX, US
Satyendra S. Chauhan - Sugarland TX, US
Masood Murtuza - Sugarland TX, US
Thomas D. Bonifield - Dallas TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21/4763

US Classification:

438629, 257E21514

Abstract:

A method of forming a semiconductor device includes an integrated circuit (IC) die which is provided with a substrate with surfaces. At least one through substrate via (TSV) is formed through the substrate to a protruding integral tip that includes sidewalls and a distal end. A metal layer is formed on the bottom surface of the IC die, and the sidewalls and the distal end of the protruding integral tips. Completing fabrication of at least one functional circuit including at least one ground pad on the top surface of the semiconductor, wherein the ground pad is coupled to said TSV.

US Patent:

8436475, May 7, 2013

Filed:

Apr 11, 2012

Appl. No.:

13/444508

Inventors:

Rajiv Dunne - Murphy TX, US
Gary P. Morrison - Garland TX, US
Satyendra S. Chauhan - Sugarland TX, US
Masood Murtuza - Sugarland TX, US
Thomas D. Bonifield - Dallas TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 23/48

US Classification:

257774, 257E23174

Abstract:

A semiconductor device includes an integrated circuit (IC) die including a substrate, and a plurality of through substrate via (TSV) that extends through the substrate to a protruding integral tip and which is partially covered with a dielectric liner and partially exposed from the dielectric liner. A metal layer is on the bottom surface of the IC die physically connecting the plurality of TSVs and physically and electrically connected to connecting the first metal protruding tips of TSVs.

US Patent:

20020114143, Aug 22, 2002

Filed:

Jan 3, 2002

Appl. No.:

10/034827

Inventors:

Gary Morrison - Garland TX, US
Darvin Edwards - Garland TX, US
Leslie Stark - Dallas TX, US

International Classification:

H05K007/06

US Classification:

361/749000, 361/782000, 174/254000, 257/724000

Abstract:

A vertical stack of semiconductor devices is formed by folding a strip-like flexible interconnector assembled with integrated circuit chips, packages and/or passive components and attaching coupling members solderable to other parts (FIGS. I4A and I4B).

US Patent:

20090061566, Mar 5, 2009

Filed:

Nov 3, 2008

Appl. No.:

12/263683

Inventors:

GREGORY E. HOWARD - Dallas TX, US
NAVIN KALIDAS - Houston TX, US
PAUL J. HUNDT - Garland TX, US
GARY P. MORRISON - Garland TX, US

Assignee:

TEXAS INSTRUMENTS INCORPORATED - Dallas TX

International Classification:

H01L 21/56
H05K 3/00

US Classification:

438127, 29842, 257E21502

Abstract:

Semiconductor chip () of a ball grid array device () is mounted onto tape substrate () using attach adhesive (). The metal layer on the top surface of substrate () uses between about 30% to 90% of its area for connecting lines (), and only the remainder for members/rings () and terminals (). Routing of differential pair signals and large numbers of signals on a single layer tape package are feasible. This embodiment creates an inexpensive high performance tape ball grid array package for chip-scale devices. Terminals () serve the connection (by bonding wires or reflow bumps) to the chip contact pads. Inserted in members/rings () are the conductive pins (), which serve as anchors for the solder bodies/balls (). Pins () are substantially insensitive to the thermomechanical stresses, which occur in device () during assembly, testing and operation.