Gary E Morrison

US Patent:

6418489, Jul 9, 2002

Filed:

Jan 18, 2000

Appl. No.:

09/488368

Inventors:

Kristen L. Mason - Austin TX
Gary R. Morrison - Austin TX
Jeffrey M. Polega - Austin TX
Donald L. Tietjen - Austin TX
Frank C. Galloway - Dripping Springs TX
Charles Edward Nuckolls - Austin TX
Jennifer L. McKeown - Austin TX
Robert Bradford Cohen - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

G06F 1328

US Classification:

710 22, 710 54, 710266, 711100, 711105, 711169

Abstract:

Direct memory access controller (DMA) ( ) adapted to directly execute C language style FOR tasks, where the FOR task includes a movement of a data element from a first location to a second location in memory, and the movement is controlled by a master DMA engine (MDE) ( ). A master DMA engine (MDE) ( ) includes a top level state machine ( ) to coordinate a context save state machine ( ), a parse state machine ( ), and a running state machine ( ). An loop control descriptor (LCD) queue ( ) and a data routing descriptor (DRD) cache store information. The LCD queue allows pipelining of descriptor parsing, while the DRD cache avoids refetching of DRDs on reentry of loops.

US Patent:

6421744, Jul 16, 2002

Filed:

Oct 25, 1999

Appl. No.:

09/426009

Inventors:

Gary R. Morrison - Austin TX
Kristen L. Mason - Austin TX
Frank C. Galloway - Dripping Springs TX
Charles E. Nuckolls - Austin TX
Jennifer L. McKeown - Austin TX
Jeffrey M. Polega - Austin TX
Donald L. Tietjen - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

G06F 928

US Classification:

710 22, 710 68, 710 23, 710 31, 710 33, 711148, 711162, 711202

Abstract:

Direct memory access controller (DMAC) ( ) adapted to directly execute C language style FOR tasks assigned by a processor ( ), where the FOR task includes a movement of a data element from a first location to a second location in memory. The DMAC includes multiple execution units (EUs) ( ), each to perform an arithmetic or logical operation, and a FOR task controller ( ) to perform the data movement. The FOR task controller selects the operation to be performed by the EU. In one embodiment, the FOR task is made up of C language type FOR loops, where descriptors identify the control and body of the loop. The descriptors identify the source of operands for an EU, and the source may be changed within a FOR task. A descriptor specifies a function code for an EU and may specify multiple sets of operands for the EU.

US Patent:

6542940, Apr 1, 2003

Filed:

Jan 18, 2000

Appl. No.:

09/488367

Inventors:

Gary R. Morrison - Austin TX
Peter J. Myers - Austin TX
Charles Edward Nuckolls - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

G06F 1328

US Classification:

710 22, 710 58, 713502, 714 47

Abstract:

Method for maintaining an execution interval for a task requestor to a DMA. A timer is provided with two counters, one ( ) to maintain the execution interval and the second ( ) to track the execution time of a task in the DMA. Each task has a predetermined execution time allowance. A task acknowledge (TACK) signal enables the tracking. A task request signal (TREQ) is generated during each execution interval until the execution time allowance is completed. The length of the second counter is less than the first counter. In one embodiment, if the first counter expires before the execution time allowance is completed, a task error signal (TERR) is illustrated.

US Patent:

6581086, Jun 17, 2003

Filed:

Jan 18, 2000

Appl. No.:

09/488366

Inventors:

Gary R. Morrison - Austin TX
Charles Edward Nuckolls - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

G06F 738

US Classification:

708523

Abstract:

A multiply and accumulate (MAC) unit ( ) having a multiplier ( ) and an adder ( ) for providing a calculated result of a MAC operation, an accumulator ( ) for storing the calculated result, and a scaler unit ( ) for selecting a subset of the calculated result stored in the accumulator. The scaler unit receives information defining the subset as a predetermined number of contiguous bits and defining the location of the bits with respect to a radix point. In response to a detected error in the selection of the subset, the scaler unit selects a second subset, where the second subset also has a predetermined number of contiguous bits having a different location with respect to the radix point:.

US Patent:

6675235, Jan 6, 2004

Filed:

Jan 18, 2000

Appl. No.:

09/488363

Inventors:

Frank C. Galloway - Dripping Springs TX
Kristen L. Mason - Austin TX
Gary R. Morrison - Austin TX
Charles Edward Nuckolls - Austin TX
Jennifer L. McKeown - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

G06F 1314

US Classification:

710 29, 712209, 712210, 364200

Abstract:

An execution unit ( ) interface protocol allowing flow-through of data, where a function is specified once and the execution unit performs the function for multiple sets of input data. Function execution is pipelined through the execution unit, where an input unit ( ) stores information, while a function logic unit ( ) processes data and an output unit ( ) holds results to be output. The execution unit ( ) allows for data rate distortion, in applications such as data compression, where the amount of data received is different from the amount of data generated as output.

US Patent:

7444568, Oct 28, 2008

Filed:

Feb 16, 2006

Appl. No.:

11/355681

Inventors:

Gary R. Morrison - Austin TX, US
Jose A. Lyon - Austin TX, US
William C. Moyer - Dripping Springs TX, US
Anthony M. Reipold - Austin TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

G01R 31/28

US Classification:

714726, 714738

Abstract:

A method for testing at least one logic block of a processor includes, during execution of a user application by the processor, the processor generating a stop and test indicator. In response to the generation of the stop and test indicator, stopping the execution of the user application and, if necessary, saving a state of the at least one logic block of the processor. The method further includes applying a test stimulus for testing the at least one logic block of the processor. The test stimulus may be shifted into scan chains so as to perform scan testing of the processor during normal operation, such as during execution of a user application.

US Patent:

7790597, Sep 7, 2010

Filed:

Jun 6, 2008

Appl. No.:

12/134337

Inventors:

Satyendra S. Chauhan - Sugar Land TX, US
Rajiv C. Dunne - Murphy TX, US
Gary P. Morrison - Garland TX, US
Masood Murtuza - Sugar Land TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 23/48
H01L 21/44

US Classification:

438613, 257737, 257738, 257E2301, 257E23023, 257E21476, 438614, 438615, 438616

Abstract:

A method used during the formation of a semiconductor device assembly can include contacting an end of a conductive bump (which can be a pillar, ball, pad, post, stud, or lead as well as other types of bumps) with a conductive powder such as a solder powder to adhere the conductive powder to the end of the bump. The powder can be flowed, for example by heating, to distribute it across the end of the bump. The flowed powder can be placed in contact with a conductive pad of a receiving substrate and can then be reflowed to facilitate electrical connection between the bump and the conductive pad.

US Patent:

8312331, Nov 13, 2012

Filed:

Apr 16, 2009

Appl. No.:

12/425101

Inventors:

Gary R. Morrison - Austin TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

G11C 29/00

US Classification:

714719

Abstract:

A method of testing a memory includes generating a plurality of addresses, such as a test address, accessing contents of each of the plurality of addresses and storing them in storage circuitry, performing a test on the plurality of addresses, accessing the memory test circuitry by sending an access address to snooping circuitry, determining if the access address matches at least one of the plurality of addresses and generating at least one hit indicator in response thereto, generating a snoop miss indicator, determining if the snoop miss indicator indicates a miss, if the snoop miss indicator indicates a miss, accessing the memory in response to the access address, and if the snoop miss indicator does not indicate a miss, either storing snooped data from a interconnect master to a selected portion of the storage circuitry or reading the snooped data from the selected portion of the storage circuitry to the interconnect master.