Gary L Walker

US Patent:

6996651, Feb 7, 2006

Filed:

Jul 29, 2002

Appl. No.:

10/207609

Inventors:

Ned D. Garinger - Tempe AZ, US
Martin L. Dorr - Chandler AZ, US
Mark W. Naumann - Tempe AZ, US
Gary A. Walker - Phoenix AZ, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

G06F 13/00

US Classification:

710305, 710316, 370364, 370389

Abstract:

A network with memory device address decoding that enables communication among integrated processing elements, including a network, a processing element and a bus gasket. The network transfers packets between multiple ports, where each port conforms to a consistent port interface protocol. The processing element includes a bus and a memory device programmed with the address of each port, so that a transaction on the bus indicating another port is decoded by the memory device. The bus gasket includes a bus interface that generates packets and a port interface that sends and receives the packets according to the consistent port interface protocol and that uses the decoded address as a destination port address. The memory device may be implemented in any desired manner, such as a memory management unit (MMU) or a direct memory access (DMA) device.

US Patent:

7051150, May 23, 2006

Filed:

Jul 29, 2002

Appl. No.:

10/207600

Inventors:

Mark W. Naumann - Tempe AZ, US
Gary A. Walker - Phoenix AZ, US
Ned D. Garinger - Tempe AZ, US
Martin L. Dorr - Chandler AZ, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

G06F 13/00

US Classification:

710317, 710 38, 710307, 710316

Abstract:

A scalable network for supporting an application using processing elements including ports, an interconnect, port interfaces, and an arbiter. Each port conforms to a consistent port interface protocol regardless of number of ports, frequency of operation, maximum datum width or data path concurrency. The interconnect has a scalable maximum datum width and a scalable data path concurrency, and includes selectable data paths between any two ports to enable transfer of datums between the ports. Each port interface formulates packets for transmission and receives packets via the corresponding port and the interconnect, where each packet includes one or more datums. The arbiter controls packet transfer via the interconnect between source and destination ports. The interconnect has a scalable data path concurrency. Pipeline stages may be added to support a selected clock frequency.

US Patent:

7139860, Nov 21, 2006

Filed:

Jul 29, 2002

Appl. No.:

10/207588

Inventors:

Gary A. Walker - Phoenix AZ, US
Ned D. Garinger - Tempe AZ, US
Martin L. Dorr - Chandler AZ, US
Mark W. Naumann - Tempe AZ, US

Assignee:

Freescale Semiconductor Inc. - Austin TX

International Classification:

G06F 13/36
G06F 5/00

US Classification:

710306, 710 45, 710311

Abstract:

An OCN with independent logical and physical layers for enabling communication among integrated processing elements, including ports, bus gaskets and a physical layer interface. Each bus gasket includes a processor element interface and a port interface. Each processor element interface of at least two bus gaskets operates according to a first logical layer protocol. Each port interface operates according to a consistent port interface protocol by sending transaction requests and receiving acknowledgements and by sending and receiving packet datums via the corresponding port. The physical layer interface transfers packets between the ports and includes an arbiter and an interconnect coupled to each port. Additional bus gaskets may be added that operate according to a second logical layer protocol which may or may not be compatible with the first. Any bus gasket may be added that is configured to communicate using multiple logical layer protocols.

US Patent:

7200137, Apr 3, 2007

Filed:

Jul 29, 2002

Appl. No.:

10/207459

Inventors:

Martin L. Dorr - Chandler AZ, US
Mark W. Naumann - Tempe AZ, US
Gary A. Walker - Phoenix AZ, US
Ned D. Garinger - Tempe AZ, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H04L 12/28

US Classification:

370351, 370396

Abstract:

A network that maximizes interconnect utilization between integrated processing elements, including ports, an interconnect, port interfaces, and an arbiter. Each port includes arbitration and data interfaces. The interconnect includes selectable data paths between the ports for packet datum transfer. Each port interface includes processing, source and destination interfaces. The source interface submits transaction requests and provides packet datums upon receiving an acknowledgement. The destination interface receives packet datums via a number of available input buffers. Each transaction request includes a transaction size, a packet priority, and a destination port address. The arbiter includes a request queue and a buffer counter for each port and a datum counter for each acknowledged transaction. The arbiter arbitrates among transaction requests based on a selected arbitration scheme, destination buffer availability, data path availability, and priority, and uses the packet datum counters, arbitration latency and data path latency to minimize dead cycles in the interconnect.

US Patent:

7277449, Oct 2, 2007

Filed:

Jul 29, 2002

Appl. No.:

10/207298

Inventors:

Ned D. Garinger - Tempe AZ, US
Martin L. Dorr - Chandler AZ, US
Mark W. Naumann - Tempe AZ, US
Gary A. Walker - Phoenix AZ, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H04L 12/28

US Classification:

370419, 370362

Abstract:

An OCN for integrated processing elements including a network with multiple ports and multiple port interfaces. The ports and the port interfaces conform to a consistent port protocol. Each port interface converts information between bus transactions of a corresponding processing element and network packets and exchanges network packets with other port interfaces. Each port includes an arbitration interface and a data interface and the network includes an interconnect and an arbiter. The interconnect includes selectable data paths between the ports for packet datum transfer. A port source interface submits transaction requests and provides packet datums upon receiving an acknowledgement. A port destination interface receives packet datums via available input buffers. Each transaction request includes a transaction size and a destination port address. The arbiter receives transaction requests, arbitrates among transaction requests, provides acknowledgements and controls the interconnect to select data paths between sources and destinations.

US Patent:

57548676, May 19, 1998

Filed:

Mar 20, 1996

Appl. No.:

8/619924

Inventors:

Gary Walker - Phoenix AZ

Assignee:

VLSI Technology, Inc. - San Jose CA

International Classification:

G06F 132

US Classification:

395750

Abstract:

A method for maximizing the performance versus the power consumption of a computer system. The method uses a CPU which has the ability to select an optimum external to internal clock frequency ratio. By changing the external to internal clock frequency ratio, the computer system is able to decrease the internal clock frequency in order to conserve power, while allowing the external clock frequency to be at an optimum level in order to maintain maximum system performance.

US Patent:

59681446, Oct 19, 1999

Filed:

Jun 27, 1996

Appl. No.:

8/673243

Inventors:

Gary Walker - Phoenix AZ
James J. Jirgal - Chandler AZ
Rishi Nalubola - Phoenix AZ
Franklyn H. Story - Chandler AZ

Assignee:

VLSI Technology, Inc. - San Jose CA

International Classification:

G06F 1328

US Classification:

710 28

Abstract:

The present invention relates to a system and method for supporting DMA I/O devices. A PCI-PCI bridge is provided to support DMA I/O devices on the PCI bus. Through the use of two signal lines and a serial link, DMA transfers may be accomplished over the PCI bus. A PCI-ISA dock bridge is also provided to allow the system to support DMA I/O devices and ISA masters (i. e. , any device including DMA I/O devices on the ISA bus that generates ISA cycles) on the ISA bus.

US Patent:

57685711, Jun 16, 1998

Filed:

Aug 29, 1996

Appl. No.:

8/705356

Inventors:

Gary Walker - Phoenix AZ
James J. Jirgal - Chandler AZ

Assignee:

VLSI Technology, Inc. - San Jose CA

International Classification:

G06F 108

US Classification:

395556

Abstract:

A system for altering a clock frequency to a logic controlling device that controls logic which runs at a fixed frequency slower than a frequency of a computer system running the logic. The system speeds up the clock signal to a logic controller when the logic controller is arbitrating between different operational requests. When the logic controller acknowledges a specific operational request, the clock controller immediately slows the clock signal down in order to allow a command strobe length that the logic device executing a specific operation request requires.

Address:

6841 Old Tarlton Pike, Circleville, OH 43113

VIN:

3FAHP07ZX7R155397

Make:

FORD

Model:

FUSION

Year:

2007