Gaurav G Mehta

US Patent:

6341099, Jan 22, 2002

Filed:

Sep 29, 2000

Appl. No.:

09/672950

Inventors:

Sudarshan Kumar - Freemont CA
Sadhana Madhyastha - Santa Clara CA
Gaurav G. Mehta - Folsom CA
Jiann-Cherng James Lan - San Jose CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G11C 700

US Classification:

365227, 365154, 36523005

Abstract:

A technique for reducing power consumption in a data storage device consisting of a number of data cells includes arranging the number of data cells in clusters, each cluster having more than one data cell having their data enable inputs connected together. A data write bus is provided to provide data enable signals to the data enable inputs of the number of data cells. A number of pass gates are respectively disposed between the clusters and the write data bus. The pass gates are selectively enabled to allow data enable signals to pass from the write data bus to the data enable inputs of the more than one data cell of a selected one or more of the clusters. A number of inverters may be respectively disposed between the number of pass gates and the clusters. A number of sustainer circuits may be respectively connected to the number of pass gates. Each of the pass gates may include a pair of field effect transistors which may be complementary field effect transistors.

US Patent:

6593776, Jul 15, 2003

Filed:

Aug 3, 2001

Appl. No.:

09/922434

Inventors:

Sudarshan Kumar - Fremont CA
Gaurav Mehta - Folsom CA
Vivek Joshi - Sunnyvale CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H03K 1994

US Classification:

326105, 326106, 326107, 326108

Abstract:

A decoder includes multiple decode gates, each to provide one bit of a decoded output signal. At least two of the decode gates share a transistor. According to one aspect, each of the multiple decode gates is a skewed gate.

US Patent:

6628539, Sep 30, 2003

Filed:

May 31, 2001

Appl. No.:

09/872975

Inventors:

Sudarshan Kumar - Fremont CA
Gaurav G. Mehta - Folsom CA
Sadhana Madhyastha - Los Altos CA
Jiann-Cherng Lan - San Jose CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G11C 1900

US Classification:

365 78, 365154, 36518912, 365240, 711127

Abstract:

A multi-entry register file cell includes multiple memory elements. A value stored in each of the multiple memory elements may be individually read from the register file cell in response to asserting a single word line.

US Patent:

6629194, Sep 30, 2003

Filed:

May 31, 2001

Appl. No.:

09/872965

Inventors:

Sudarshan Kumar - Fremont CA
Gaurav G. Mehta - Folsom CA
Sadhana Madhyastha - Los Altos CA
Jiann-Cherng Lan - San Jose CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1200

US Classification:

711104, 711 5, 36518525, 36523003, 36523066

Abstract:

A memory includes a plurality of banks of memory elements. For a memory read access operation, bank enable logic coupled to each of the plurality of banks is responsive to an address of a memory element to be read to selectively deactivate a first precharge clock signal to be received by a first one of the banks that includes the memory element to be read. The bank enable logic is further responsive to the address to selectively maintain in an active state a second precharge clock signal to be received by a second one of the banks that does not include the memory element to be read.

US Patent:

6631093, Oct 7, 2003

Filed:

Jun 29, 2001

Appl. No.:

09/895361

Inventors:

Sudarshan Kumar - Fremont CA
Jiann-Cherng Lan - San Jose CA
Wenjie Jiang - San Jose CA
Gaurav Mehta - Folsom CA
Sadhana Madhyastha - Santa Clara CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G11C 700

US Classification:

365203, 365204

Abstract:

A low power memory bit line precharge scheme. A memory bit line is coupled to a first read precharge device. A second write precharge device is also coupled to the memory bit line and is to be enabled only in response to a memory write operation. The first read and second write precharge devices are sized such that their combined drive strength is sufficient to precharge the first memory bit line during a precharge period following a write operation.

US Patent:

60054174, Dec 21, 1999

Filed:

Jun 30, 1997

Appl. No.:

8/885120

Inventors:

Gaurav G. Mehta - Folsom CA
Yahya Sotoudeh - San Jose CA
Chris L. Simone - San Jose CA
Chi-Kai Sin - San Jose CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H03K 19096

US Classification:

326 98

Abstract:

A method and apparatus for reducing power consumption in a domino logic is provided. An input of the domino logic block has as an output of an upstream logic block. A first state, e. g. default or idle, of the output of the upstream logic block is determined. The an output of the domino logic block corresponding to the said first state is determined. A logic block is modified, such that the output of the domino logic block for the first state is the same as a precharge state of the output. This results in preventing the output of the domino logic block from toggling when the first state is the input to the domino logic block.

US Patent:

58806083, Mar 9, 1999

Filed:

Dec 27, 1996

Appl. No.:

8/774261

Inventors:

Gaurav G. Mehta - San Jose CA
David Harris - Stanford CA
S. Deo Singh - Fremont CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H03K 1900
H03K 19096

US Classification:

326 93

Abstract:

The present invention is a novel method of interfacing static logic to domino logic. A static logic block is connected to one input of a domino evaluation tree. The domino evaluation tree operates only during a brief window of time, while an evaluation control block is ON. Since the input to the domino gate only must be stable during this brief window of time, there is no need to latch the output of the static logic.

US Patent:

58217754, Oct 13, 1998

Filed:

Dec 27, 1996

Appl. No.:

8/774262

Inventors:

Gaurav G. Mehta - San Jose CA
David Harris - Stanford CA
S. Deo Singh - Fremont CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H03K 19096

US Classification:

326 98

Abstract:

The present invention is an improved interface between monotonic and non-monotonic domino logic. A monotonic domino logic block is clocked by CLK. The last stage of the monotonic domino logic is clocked by the delayed clock, DCLK, to extend its evaluation period beyond Phase I by a brief window of time, t. sub. d. The true output and the inverted output of the last stage of the monotonic domino logic block are inputs to a non-monotonic domino evaluation tree. The non-monotonic domino evaluation tree operates while an evaluation control block is ON. The evaluation control block is ON only during that extension of the evaluation period, t. sub. d, for a time less than or equal to the period t. sub. d. Since the output of the last stage of the monotonic logic block remains stable during this extended evaluation period, and the non-monotonic domino evaluation tree operates at most during this window of time, there is no need to use latches or use a dual rail implementation for the monotonic logic.