Gaurav A Mehta

US Patent:

20180089094, Mar 29, 2018

Filed:

Sep 23, 2016

Appl. No.:

15/274644

Inventors:

- San Diego CA, US
Gaurav MEHTA - Oviedo FL, US
Spencer Ellis WILLIAMS - Raleigh NC, US
Brian Michael STEMPEL - Raleigh NC, US
Thomas Philip SPEIER - Wake Forest NC, US
Michael Scott MCILVAINE - Raleigh NC, US
William James MCAVOY - Raleigh NC, US

International Classification:

G06F 12/0891
G06F 12/0895
G06F 12/1045

Abstract:

Systems and methods for precise invalidation of cache lines of a virtually indexed virtually tagged (VIVT) cache include associating, with each cache line of the VIVT cache, at least a translation lookaside buffer (TLB) index corresponding to a TLB entry which comprises a virtual address to physical address translation for the cache line. The TLB entries are inclusive of the cache lines of the VIVT cache. Upon receiving an invalidate instruction, the invalidate instruction is filtered at the TLB to determine if the invalidate instruction might affect cache lines in the VIVT cache. If the invalidate instruction might affect cache lines in the VIVT cache, the TLB indices of the TLB entries which match the invalidate instruction are determined, and only the cache lines of the VIVT cache which are associated with the affected TLB indices are selectively invalidated.

US Patent:

20170046266, Feb 16, 2017

Filed:

Mar 30, 2016

Appl. No.:

15/084773

Inventors:

- San Diego CA, US
Gaurav Mehta - Morrisville NC, US
Robert Douglas Clancy - Cary NC, US

International Classification:

G06F 12/08

Abstract:

Described herein are apparatuses, methods, and computer readable media for way mispredict mitigation on a way predicted set-associative cache. A way prediction array may be accessed while searching the cache for data. A predicted way to search for the data may be determined from the way prediction array. If the search for the data in the predicted way results in a miss, a first prediction index associated with a cache line in the predicted way may be determined. The first prediction index may be compared to a second prediction index. The second prediction index may be associated with a search address being used for accessing the cache during execution of an instruction. If there is a match, the predicted way may be selected as a victim way.

US Patent:

20170046278, Feb 16, 2017

Filed:

Mar 29, 2016

Appl. No.:

15/083978

Inventors:

- San Diego CA, US
Gaurav MEHTA - Morrisville NC, US
Michael Scott MCILVAINE - Raleigh NC, US
William Robert FLEDERBACH - Raleigh NC, US

International Classification:

G06F 12/12
G06F 12/08

Abstract:

Techniques and apparatus are provided for updating replacement policy information for a fully associative buffer cache. A method is provided that generally includes updating replacement policy information for entries in a second cache memory based on hits indicating corresponding set-matching entries are present in the first cache memory, and evicting entries from the second cache memory based on the updated replacement policy information.