Gaurav Verma

US Patent:

6387803, May 14, 2002

Filed:

Sep 21, 1998

Appl. No.:

09/158346

Inventors:

Somit Talwar - Palo Alto CA
Gaurav Verma - Palo Alto CA
Karl-Josef Kramer - Vaihingen, DE
Kurt Weiner - San Jose CA

Assignee:

Ultratech Stepper, Inc. - San Jose CA

International Classification:

H01L 2144

US Classification:

438682, 438533, 438586, 438592, 438619, 438623, 438680

Abstract:

The invented method produces a silicide region on a silicon body that is useful for a variety of purposes, including the reduction of the electrical contact resistance to the silicon body or an integrated electronic device formed thereon. The invented method includes a step of producing an amorphous region on the silicon body using ion implantation, for example, a step of forming a metal layer such as titanium, cobalt or nickel in contact with the amorphous region, and a step of irradiating the metal with intense light from a source such as a laser, to cause metal atoms to diffuse into the amorphous region to form an alloy region with a silicide composition. In an application of the invented method to the manufacture of a MISFET device, the metal layer is preferably formed with a thickness that is at least sufficient to produce a stoichiometric proportion of metal and silicon atoms in the amorphous region of the gate of the MISFET device. Importantly, the irradiating step proceeds until the metal overlying the gate alloy region is consumed and the gate alloy region is exposed. The gate alloy region has a higher reflectivity than the metal layer, and thus reduces further thermal loading of the gate alloy region so that silicide growth can be continued in the source and drain regions without adversely impacting the gate of the MISFET device.

US Patent:

6642726, Nov 4, 2003

Filed:

Oct 30, 2001

Appl. No.:

10/000114

Inventors:

Kurt H. Weiner - San Jose CA
Gaurav Verma - Atherton CA
Isabella T. Lewis - San Jose CA

Assignee:

KLA-Tencor Corporation - San Jose CA

International Classification:

G01R 31305

US Classification:

324751, 324 96, 250311, 2504922, 356456, 382149

Abstract:

Disclosed are methods and apparatus for automatically filtering out physical defects from electrical defects that are found during a voltage contrast inspection of a test structure on a semiconductor device.

US Patent:

6732002, May 4, 2004

Filed:

Nov 14, 2001

Appl. No.:

09/991188

Inventors:

Kurt H. Weiner - San Jose CA
Gaurav Verma - Atherton CA

Assignee:

KLA-Tencor Corporation - San Jose CA

International Classification:

G06F 1900

US Classification:

700110, 702183

Abstract:

Disclosed are methods and apparatus for sampling defects. A test chip having a plurality of test structures is provided that is designed so that defect sampling may be customized to obtain different critical areas from the test chip. Each test structure is conceptually divided into a plurality of unit cells (e. g. , a pair of grounded and floating conductive lines). The defects of a percentage of unit cells may then be sampled for each test structure to conceptually form a sub test structure that has a different size than the original test structure. The percentage of unit cells that are sampled for each test structure is chosen so as to achieve a specific critical area curve. The defects from each sampled set of unit cells may then combined to determine yield for a product chip having the same specific critical area curve. These defect sampling techniques are customizable for different product chips having different critical areas to thereby predict product yield for such product chips using the same test chip. In general terms, a first set of unit cells may be sampled from the test structures to predict yield for a product chip having a first critical area, and a second different set of unit cells may be sampled to predict yield for a product chip having a second critical area.

US Patent:

6861666, Mar 1, 2005

Filed:

Oct 17, 2002

Appl. No.:

10/282322

Inventors:

Kurt H. Weiner - San Jose CA, US
Gaurav Verma - Atherton CA, US
Peter D. Nunan - Monte Sereno CA, US
Indranil De - San Jose CA, US

Assignee:

KLA-Tencor Technologies Corporation - Milpitas CA

International Classification:

H01L023/58

US Classification:

257 48, 257775

Abstract:

Disclosed is test structure that can be fabricated with minimal photolithography masking steps and in which defects may be localized to specific layers. Mechanisms for fabricating such test structures are also provided. In one embodiment, a semiconductor test structure suitable for a voltage contrast inspection is provided. The test structure includes one or more test layers corresponding to one or more product layers selected from a plurality of product layers of an integrated circuit (IC) product structure. The number of the selected one or more test layers is less than a total number of the plurality of product layers of the product structure, and the test layers include at least a first portion that is designed to have a first potential during the voltage contrast inspection and a second portion that is designed to have a second potential during the voltage contrast inspection. The first potential differs from the second potential. The selected one or more test layers which correspond to product layers are selected from the plurality of product layers such that defects found in the test layers of the test structure during the voltage contrast inspection represent a prediction of defects in the corresponding product structure.

US Patent:

6995393, Feb 7, 2006

Filed:

Oct 2, 2002

Appl. No.:

10/265051

Inventors:

Kurt H. Weiner - San Jose CA, US
Gaurav Verma - Atherton CA, US

Assignee:

KLA-Tencor Technologies Corporation - Milpitas CA

International Classification:

H01L 23/58

US Classification:

257 48, 438 18

Abstract:

An improved voltage contrast test structure is disclosed. In general terms, the test structure can be fabricated in a single photolithography step or with a single reticle or mask. The test structure includes substructures which are designed to have a particular voltage potential pattern during a voltage contrast inspection. For example, when an electron beam is scanned across the test structure, an expected pattern of intensities are produced and imaged as a result of the expected voltage potentials of the test structure. However, when there is an unexpected pattern of voltage potentials present during the voltage contrast inspection, this indicates that a defect is present within the test structure. To produce different voltage potentials, a first set of substructures are coupled to a relatively large conductive structure, such as a large conductive pad, so that the first set of substructures charges more slowly than a second set of substructures that are not coupled to the relatively large conductive structure. Mechanisms for fabricating such a test structure are also disclosed.

US Patent:

7067335, Jun 27, 2006

Filed:

Oct 2, 2002

Appl. No.:

10/264625

Inventors:

Kurt H. Weiner - San Jose CA, US
Gaurav Verma - Atherton CA, US

Assignee:

KLA-Tencor Technologies Corporation - Milpitas CA

International Classification:

G01R 31/26
H01L 21/66

US Classification:

438 16, 324765

Abstract:

An improved voltage contrast test structure is disclosed. In general terms, the test structure can be fabricated in a single photolithography step or with a single reticle or mask. The test structure includes substructures which are designed to have a particular voltage potential pattern during a voltage contrast inspection. For example, when an electron beam is scanned across the test structure, an expected pattern of intensities are produced and imaged as a result of the expected voltage potentials of the test structure. However, when there is an unexpected pattern of voltage potentials present during the voltage contrast inspection, this indicates that a defect is present within the test structure. To produce different voltage potentials, a first set of substructures are coupled to a relatively large conductive structure, such as a large conductive pad, so that the first set of substructures charges more slowly than a second set of substructures that are not coupled to the relatively large conductive structure. Mechanisms for fabricating such a test structure are also disclosed.

US Patent:

7198963, Apr 3, 2007

Filed:

Aug 8, 2003

Appl. No.:

10/638027

Inventors:

Gaurav Verma - Atherton CA, US
Kurt H. Weiner - San Jose CA, US

Assignee:

KLA-Tencor Technologies Corporation - Milpitas CA

International Classification:

H01L 21/66

US Classification:

438 14, 438 16, 438 17, 257E21525

Abstract:

Disclosed are techniques for efficiently inspecting defects on voltage contrast test. In one embodiment, methodologies and test structures allow inspection to occur entirely within a charged particle system. In a specific embodiment, a method of localizing and imaging defects in a semiconductor test structure suitable for voltage contrast inspection is disclosed. A charged particle beam based tool is used to determine whether there are any defects present within a voltage contrast test structure. The same charged particle beam based tool is then used to locate defects determined to be present within the voltage contrast test structure. Far each localized defect, the same charged particle beam based tool may then be used to generate a high resolution image of the localized defect whereby the high resolution image can later be used to classify the each defect. In one embodiment, the defect's presence and location are determined without rotating the test structure relative to the charged particle beam.

US Patent:

7280945, Oct 9, 2007

Filed:

Jul 1, 2002

Appl. No.:

10/187567

Inventors:

Kurt H. Weiner - San Jose CA, US
Gaurav Verma - Atherton CA, US
Indranil De - San Jose CA, US

Assignee:

KLA-Tencor Technologies Corporation - Milpitas CA

International Classification:

G06F 17/10
G06F 17/50

US Classification:

703 2, 700110, 716 21

Abstract:

Disclosed are mechanisms are provided for determining whether a particular integrated circuit (IC) pattern is susceptible to systematic failure, e. g. , due to process fluctuations. In one embodiment, final resist patterns for such IC pattern are simulated using a sparse type simulator under various process settings. The sparse type simulator uses a model (e. g. , a variable threshold resist model) for a particular photolithography process in which the IC pattern is to be fabricated. The model is generated from measurements taken from a plurality of simulated structures output from a rigorous type simulator. The simulated final resist patterns may then be analyzed to determine whether the corresponding IC pattern is susceptible to systematic failure. After an IC pattern which is susceptible to systematic failure has been found, a test structure may be fabricated from a plurality of IC patterns or cells. The cells of the test structure are arranged to have a particular pattern of voltage potential or brightness levels during a voltage contrast inspection.