Gavin L Huggins

US Patent:

20100100691, Apr 22, 2010

Filed:

Oct 18, 2008

Appl. No.:

12/253967

Inventors:

Harold B Noyes - Boise ID, US
Mark Jurenka - Boise ID, US
Gavin Huggins - Meridian ID, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G06F 12/00

US Classification:

711154, 711E12001

Abstract:

Systems and methods are provided for managing access to registers. In one embodiment, a system may include a processor and a plurality of registers. The processor and the plurality of registers may be integrated into a single device, or may be in separate devices. The plurality of registers may include a first set of registers that are directly accessible by the processor, and a second set of registers that are not directly accessible by the processor. The second set of registers may, however, be accessed indirectly by the processor via the first set of registers. In one embodiment, the first set of registers may include a register for selecting a register bank from the second set of registers, and a register for selecting a particular address within the register bank, to allow indirect access by the processor to the registers of the second set.

US Patent:

20100100714, Apr 22, 2010

Filed:

Oct 18, 2008

Appl. No.:

12/253966

Inventors:

Harold B Noyes - Boise ID, US
Mark Jurenka - Boise ID, US
Gavin Huggins - Meridian ID, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G06F 9/305
G06F 9/30

US Classification:

712223, 712220, 712E09018, 712E09023

Abstract:

Systems and methods are provided for managing access to registers. A system may include a set of direct registers and a set of indirect registers. The indirect registers may be accessed through the direct registers, and the direct registers may provide various features to provide faster access to the indirect registers. One of the direct registers may indicate access modes for accessing the indirect registers. The access modes may include auto-increment, auto-decrement, auto-reset, and no change modes. Based on the access mode, the currently accessed address may be automatically modified after accessing the indirect register at the address.

US Patent:

20120265970, Oct 18, 2012

Filed:

Jun 22, 2012

Appl. No.:

13/531077

Inventors:

Harold B Noyes - Boise ID, US
Mark Jurenka - Boise ID, US
Gavin Huggins - Meridian ID, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G06F 9/30

US Classification:

712220, 712E09016

Abstract:

Systems and methods are provided for managing access to registers. A system may include a set of direct registers and a set of indirect registers. The indirect registers may be accessed through the direct registers, and the direct registers may provide various features to provide faster access to the indirect registers. One of the direct registers may indicate access modes for accessing the indirect registers. The access modes may include auto-increment, auto-decrement, auto-reset, and no change modes. Based on the access mode, the currently accessed address may be automatically modified after accessing the indirect register at the address.

US Patent:

20200192840, Jun 18, 2020

Filed:

Feb 24, 2020

Appl. No.:

16/799484

Inventors:

- Boise ID, US
Gavin L. Huggins - Meridian ID, US

International Classification:

G06F 13/28
G06F 13/10
G06F 13/42
G06F 13/40
G06F 15/78

Abstract:

A system includes a processor and a hardware accelerator coupled to the processor. The hardware accelerator includes data analysis elements configured to analyze a data stream based on configuration data and to output a result, and an integrated circuit device that includes a DMA engine that writes input data to and read output data from the data analysis elements, one or more preprocessing cores that receive the input data from the DMA engine prior to the DMA engine writing the input data to the one or more data analysis elements and perform custom preprocessing functions on the input data, and one or more post-processing cores that receive the output data from the DMA engine after the output data is read from the data analysis elements but prior to the output data being output to the processor and perform custom post-processing functions on the output data.

US Patent:

20180113825, Apr 26, 2018

Filed:

Jan 18, 2017

Appl. No.:

15/409351

Inventors:

- Boise ID, US
Gavin L. Huggins - Meridian ID, US

International Classification:

G06F 13/28
G06F 13/10
G06F 13/42
G06F 13/40

Abstract:

A system includes a processor and a hardware accelerator coupled to the processor. The hardware accelerator includes data analysis elements configured to analyze a data stream based on configuration data and to output a result, and an integrated circuit device that includes a DMA engine that writes input data to and read output data from the data analysis elements, one or more preprocessing cores that receive the input data from the DMA engine prior to the DMA engine writing the input data to the one or more data analysis elements and perform custom preprocessing functions on the input data, and one or more post-processing cores that receive the output data from the DMA engine after the output data is read from the data analysis elements but prior to the output data being output to the processor and perform custom post-processing functions on the output data.

US Patent:

20170345467, Nov 30, 2017

Filed:

Aug 14, 2017

Appl. No.:

15/676796

Inventors:

- Boise ID, US
Mark Jurenka - Boise ID, US
Gavin Huggins - Meridian ID, US

International Classification:

G11C 7/10
G06F 12/06
G06F 9/30
G06F 9/34

Abstract:

Systems and methods are provided for managing access to registers. In one embodiment, a system may include a processor and a plurality of registers. The processor and the plurality of registers may be integrated into a single device, or may be in separate devices. The plurality of registers may include a first set of registers that are directly accessible by the processor, and a second set of registers that are not directly accessible by the processor. The second set of registers may, however, be accessed indirectly by the processor via the first set of registers. In one embodiment, the first set of registers may include a register for selecting a register bank from the second set of registers, and a register for selecting a particular address within the register bank, to allow indirect access by the processor to the registers of the second set.

US Patent:

20150134898, May 14, 2015

Filed:

Jan 19, 2015

Appl. No.:

14/599892

Inventors:

- Boise ID, US
Mark Jurenka - Boise ID, US
Gavin Huggins - Meridian ID, US

International Classification:

G11C 7/10
G06F 12/06

US Classification:

711109

Abstract:

Systems and methods are provided for managing access to registers. In one embodiment, a system may include a processor and a plurality of registers. The processor and the plurality of registers may be integrated into a single device, or may be in separate devices. The plurality of registers may include a first set of registers that are directly accessible by the processor, and a second set of registers that are not directly accessible by the processor. The second set of registers may, however, be accessed indirectly by the processor via the first set of registers. In one embodiment, the first set of registers may include a register for selecting a register bank from the second set of registers, and a register for selecting a particular address within the register bank, to allow indirect access by the processor to the registers of the second set.