George Robert Canepa

US Patent:

52455742, Sep 14, 1993

Filed:

Dec 23, 1991

Appl. No.:

7/812631

Inventors:

Kevin W. Frary - Fair Oaks CA
George Canepa - Folsom CA
Sherif Sweha - El Dorado Hills CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G11C 700

US Classification:

36518909

Abstract:

In a memory array having a plurality of bitlines each connected to a plurality of memory devices having a state in which current is transferred by the memory device and a state in which current is not transferred by the device, a column select device for activating each bitline, a plurality of wordlines for activating individual memory devices joined to each bitline, apparatus for providing constant current in the conducting state of a memory device connected to a bitline, a device connecting a source voltage to a plurality of bitlines, and a reference bitline for providing an output reference signal, the improvement including apparatus for providing a source of current in addition to current through the device connecting a source voltage to a plurality of bitlines in order to charge any capacitance of a selected bitline when that bitline is selected whereby switching between memory devices joined to different bitlines is accelerated.

US Patent:

51424959, Aug 25, 1992

Filed:

Mar 10, 1989

Appl. No.:

7/321887

Inventors:

George R. Canepa - Folsom CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G11C 700
G11C 11413
G11C 2900

US Classification:

36518909

Abstract:

An improvement in the margining circuit wherein a variable load is provided to a column of EPROM cells. A plurality of parallel transistors are coupled as the load and by controlling the number of transistors which are turned on, the voltage to the column can be adjusted, effectively adjusting the current to the cells.

US Patent:

46850848, Aug 4, 1987

Filed:

Jun 7, 1985

Appl. No.:

6/742459

Inventors:

George R. Canepa - Orangevale CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G11C 1300

US Classification:

365189

Abstract:

An EPROM which includes on-chip circuitry for selecting alternate addressing. An EPROM cell, separate from the memory's array, is programmed to convert the memory to the alternate page mode addressing. The selection of the pages is done through the data lines. This frees address lines when the alternate mode is selected.

US Patent:

50558978, Oct 8, 1991

Filed:

Jul 27, 1988

Appl. No.:

7/225035

Inventors:

George R. Canepa - Folsom CA
Mark A. Holler - Palo Alto CA
Simon M. Tam - San Mateo CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 2968
H01L 2702
H01L 2710
H03K 1908

US Classification:

357 235

Abstract:

A cell employing floating gate storage device particularly suited for neural networks. The floating gate from the floating gate device extends to and becomes part of a second, field effect device. Current through the second device is affected by the charge on the floating gate. The weighting factor for the cell is determined by the amount of charge on the floating gate. By charging the floating gate to various levels, a continuum of weighting factors is obtained. Multiplication is obtained since the current through the second device is a function of the weighting factor.

US Patent:

50479890, Sep 10, 1991

Filed:

Mar 10, 1989

Appl. No.:

7/321909

Inventors:

George R. Canepa - Folsom CA
Mark Bauer - Folsom CA
Phil Kliza - Folsom CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G11C 800
G06F 1206

US Classification:

3652385

Abstract:

An EPROM includes an on chip circuitry for selecting an alternative chapter mode addressing scheme. By utilizing the chapter addressing mode, a plurality of devices can be coupled in parallel, wherein each device is treated as a chapter of the total memory capacity. Hard latches are used to store a designated code and soft latches are used to latch in chapter addresses from data lines. A chapter is evaluated if values stored in the hard latch match the values inputted to the soft latch.

US Patent:

55329152, Jul 2, 1996

Filed:

Mar 23, 1994

Appl. No.:

8/217095

Inventors:

Dimitris Pantelakis - Folsom CA
Kerry Tedrow - Orangevale CA
Johnny Javanifard - Sacramento CA
George Canepa - Folsom CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H02M 318
G05F 316

US Classification:

363 60

Abstract:

A circuit for providing a regulated output voltage from a charge pump circuit while utilizing very low amounts of power, the circuit including a clock circuit for providing clock pulses to operate the charge pump circuit to produce an output voltage, a bias circuit for monitoring the output voltage of the charge pump and furnishing signals for enabling the clock circuit in response to an insufficient output voltage, and circuitry for enabling the bias circuit during a fraction of the total operating time available to the charge pump.