George W Link

US Patent:

20100253366, Oct 7, 2010

Filed:

Apr 3, 2009

Appl. No.:

12/384358

Inventors:

Craig E. Deibele - Knoxville TN, US
George Brian Link - Knoxville TN, US
Vladimir V. Peplov - Oak Ridge TN, US

International Classification:

G01R 27/28

US Classification:

324649

Abstract:

A measuring system minimizes the parasitic affects of lumped circuit elements. The system includes two or more in-situ interfaces configured to conductively link a source to an internal load and an external load. The in-situ interfaces are linked to a shunt conductor. Two or more linear and dynamic elements conductively link the in-situ interfaces in series. The dynamic elements are configured to overwhelm the parasitic self-capacitance of an input circuit coupled to at least one of the in-situ interfaces. A shield enclosing at least one of the linear and dynamic elements has a conductive surface to fields and electromagnetic interference. The shield has attenuation ratios that substantially dampen the parasitic capacitance between the linear and dynamic elements that bridge some of the in-situ interfaces.