George May

US Patent:

20120153962, Jun 21, 2012

Filed:

Dec 15, 2010

Appl. No.:

12/968864

Inventors:

Robert J. Finch - Essex Junction VT, US
George A. May - Essex Junction VT, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

International Classification:

G01N 27/60

US Classification:

324456

Abstract:

A method of implementing electrostatic discharge (ESD) testing of an integrated circuit includes applying an ESD event to an exposed backside of a substrate of the integrated circuit, wherein the backside of the substrate is electrically isolated from circuit structures formed at a front-end-of-line (FEOL) region of the integrated circuit. The operation of the circuit structures is tested to determine whether the ESD event has caused damage to one or more of the circuit structures as a result of a breakdown in the electrical isolation between the circuit structures and the backside of the substrate.