George W Nation

US Patent:

6557069, Apr 29, 2003

Filed:

Nov 12, 1999

Appl. No.:

09/439189

Inventors:

Robert Allen Drehmel - Goodhue MN
Kent Harold Haselhorst - Byron MN
Russell Dean Hoover - Rochester MN
James Anthony Marcella - Rochester MN
George Wayne Nation - Eyota MN

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1300

US Classification:

710307, 710107, 709253

Abstract:

An internal processor/memory bus contains an address portion for transmitting addresses and commands, having a series of hierarchical uni-directional links between processors and local repeaters (ARPs), and between the ARPs and a central repeater (ASW). A command propagates from a requesting device to its local ARP, to the ASW. From the ASW, the command is broadcast to all devices on the bus by transmitting to all ARPs or directly attached memory, and from the ARPs to the devices. Preferably, the ASW globally arbitrates the address bus, and all commands propagate at pre-defined clock cycles through the bus. Preferably, each device on the bus independently signals a response via a separate response link running directly to a global collector, which collects all responses and broadcasts a single system-wide response back to the devices. In the preferred embodiment, addresses/commands and data are transmitted on essentially separate paths having different topologies, and at different times, and are arbitrated separately. The data portion of the network comprises a set of bi-directional links from the processors to a local data switch unit (DSW).

US Patent:

6823502, Nov 23, 2004

Filed:

Dec 31, 2002

Appl. No.:

10/334568

Inventors:

Matthew Scott Wingren - Rochester MN
George Wayne Nation - Eyota MN
Gary Scott Delp - Rochester MN
Jonathan William Byrn - Kasson MN

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G06F 1750

US Classification:

716 9, 716 8, 716 10

Abstract:

A tool for designing an integrated circuit and semiconductor product that generates correct RTL for I/O buffer structures in consideration of the requirements of diffused configurable I/O blocks and/or I/O hardmacs of the product. Given either a slice description of a partially manufactured semiconductor product, a designer can generate the I/O resources of an application set. Then given an application set having a transistor fabric, and the diffused configurable I/O blocks and/or the I/O hardmacs, and a plurality of accompanying shells, the I/O generation tool herein automatically reads a database having the slice description and generates the I/O buffer structures from the transistor fabric. The I/O generation tool further conditions and integrates input from either or both customer having her/his own logic and requesting a specific semiconductor product or from IP cores with their preestablished logic. The I/O generation tool creates correct RTL from the transistor fabric for correct placement, timing, testing, and function of I/O buffer amplifiers for the semiconductor product, either incrementally or globally.

US Patent:

6966044, Nov 15, 2005

Filed:

Dec 9, 2002

Appl. No.:

10/316101

Inventors:

Paul G. Reuland - Rochester MN, US
George W. Nation - Eyota MN, US
Jonathan Byrn - Kasson MN, US
Gary S. Delp - Rochester MN, US

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G06F017/50

US Classification:

716 17, 716 1, 716 19, 716 20

Abstract:

A method for composing memory on a programmable platform device comprising the steps of: (A) accepting information about a programmable platform device comprising one or more diffused memory regions and one or more gate array regions; (B) accepting predetermined design information for one or more memories; and (C) composing one or more memory building blocks (i) in the one or more diffused memory regions, (ii) in the one or more gate array regions or (iii) in both the diffused memory and the gate array regions based upon the predetermined design information and the information about the programmable platform device.

US Patent:

7043611, May 9, 2006

Filed:

Dec 11, 2002

Appl. No.:

10/316510

Inventors:

Gary P. McClannahan - Rochester MN, US
Gary S. Delp - Rochester MN, US
George W. Nation - Eyota MN, US

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G06F 12/00

US Classification:

711154, 711156, 711163, 711170, 326 39

Abstract:

A reconfigurable memory controller includes a plurality of communicatively coupled memory controllers. The plurality of memory controllers may be configured into a first configuration based on a grouping of memory controllers and then reconfigured into a second configuration based on a different grouping of memory controllers, where the first and second configurations have different performance bandwidths for accessing memory.

US Patent:

7043703, May 9, 2006

Filed:

Sep 11, 2002

Appl. No.:

10/241317

Inventors:

George W. Nation - Eyota MN, US
Gary S. Delp - Rochester MN, US

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G06F 17/50

US Classification:

716 1, 716 12, 438 48, 257324

Abstract:

An apparatus comprising (i) one or more input/output cells, (ii) one or more hard macros and (iii) one or more input/output affinity regions. The one or more input/output affinity regions may be disposed between the one or more input/output cells and the one or more hard macros. Each of the one or more input/output affinity regions may be customized as (i) circuitry in a first mode and (ii) routing between the one or more input/output cells and the one or more hard macros in a second mode.

US Patent:

7055113, May 30, 2006

Filed:

Dec 31, 2002

Appl. No.:

10/335360

Inventors:

Robert Neal Carlton Broberg, III - Rochester MN, US
Jonathan William Byrn - Kasson MN, US
Gary Scott Delp - Rochester MN, US
Michael K. Eneboe - San Jose CA, US
Gary Paul McClannahan - Rochester MN, US
George Wayne Nation - Eyota MN, US
Paul Gary Reuland - Rochester MN, US
Thomas Sandoval - Los Gatos CA, US
Matthew Scott Wingren - Rochester MN, US

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G06F 17/50

US Classification:

716 1, 716 18

Abstract:

A set of tools is provided herein that produces useful, proven, and correct integrated semiconductor chips. Having as input either a customer's requirements for a chip, or a design specification for a partially manufactured semiconductor chip, the tools generate the RTL for control plane interconnect; memory composition, test, and manufacture; embedded logic analysis, trace interconnection, and utilization of spare resources on the chip; I/O qualification, JTAG, boundary scan, and SSO analysis; testable clock generation, control, and distribution; interconnection of all of the shared logic in a testable manner from a transistor fabric and/or configurable blocks in the slice. The input customer requirements are first conditioned by RTL analysis tools to quickly implement its logic. The slice definition and the RTL shell provides the correct logic for a set of logic interfaces for the design specification to connect. The tools share a common database so that logical interactions do not require multiple entries.

US Patent:

7069523, Jun 27, 2006

Filed:

Dec 13, 2002

Appl. No.:

10/318623

Inventors:

George Wayne Nation - Eyota MN, US
Gary Scott Delp - Rochester MN, US
Paul Gary Reuland - Rochester MN, US

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G06F 17/50

US Classification:

716 2, 716 6, 716 18, 714718

Abstract:

A tool for designing integrated circuits that optimizes the placement and timing of memory blocks within the circuit. Given a manufactured slice that has a number of blocks already diffused and logically integrated, the memory generation tool herein automatically considers the available diffused memory and the gate array of the slices to configure and optimize them into a customer's requirements for memory. The memory generation tool has a memory manager, a memory resource database, a memory resource selector, and a memory composer. Together these all interact to generate memories from the available memories within the memory resource database. The memory composer actually generates the RTL logic shells for the memories, and outputs the memory designs in Verilog, VHDL, or other tool synthesis language. Once a memory is created, it is tested. Upon successful testing, the memory manager updates the memory resource database to indicate the successfully tested memory is no longer available as a resource for the generation of further memories.

US Patent:

7301906, Nov 27, 2007

Filed:

Aug 30, 2002

Appl. No.:

10/232051

Inventors:

George Wayne Nation - Eyota MN, US
Gurumani Senthil - San Jose CA, US
Gary Scott Delp - Rochester MN, US

Assignee:

LSI Corporation - Milpitas CA

International Classification:

G06F 11/00
H04L 12/28

US Classification:

370235, 3702301, 370392, 370503

Abstract:

Methods and structure for standardized, high-speed serial communication to reduce memory capacity requirements within receiving elements of a high-speed serial communication channel. In an exemplary SPI compliant embodiment of the invention, the semantic meaning of the STARVING, HUNGRY and SATISFIED flow control states is modified to allow the transmitting and receiving elements to manage buffer storage in a more efficient manner to thereby reduce memory capacity requirements while maintaining the integrity of flow control contracts and commitments. The methods and structure further provide for generation of storage metric information to dynamically update the flow control status information asynchronously with respect to data packet transmissions.