George Etal Perlegos

US Patent:

42233941, Sep 16, 1980

Filed:

Feb 13, 1979

Appl. No.:

6/011915

Inventors:

Saroj Pathak - Campbell CA
George Perlegos - Cupertino CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G11C 1140

US Classification:

365210

Abstract:

An MOS sensing amplifier for sensing the binary state of floating gate memory devices in a read-only memory is disclosed. The potentials on the column lines in the memory are held to a narrow voltage swing. A pair of "zero" threshold voltage transistors having slightly different threshold voltages are used to maintain the potentials on these lines. A potential developed from the column line is compared with a reference potential developed with a "dummy" biasing network and a "dummy" floating gate memory device.

US Patent:

42662834, May 5, 1981

Filed:

Feb 16, 1979

Appl. No.:

6/012670

Inventors:

George Perlegos - Cupertino CA
William S. Johnson - Palo Alto CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

B11C 1140

US Classification:

365104

Abstract:

An electrically alterable read-mostly MOS memory (commonly referred to as E. sup. 2 PROM) employing floating gate memory devices is described. Each word stored in memory may be separately accessed for reading and writing. The memory array is arranged with additional lines and selection means to prevent the high-level programming signals from the X-decoders from programming all the floating gate devices along a selected X-line. A high voltage circuit is described which permits the handling of potentials greater than the grounded gate breakdown voltage associated with the shallow junction devices used in the memory. A unique sensing amplifier is also disclosed which detects low currents at high speeds.

US Patent:

45352593, Aug 13, 1985

Filed:

Jun 18, 1982

Appl. No.:

6/389819

Inventors:

George Smarandoiu - Palo Alto CA
George Perlegos - Fremont CA

Assignee:

Seeq Technology, Inc. - San Jose CA

International Classification:

G11C 706
G11C 900
G11C 1704
G11C 1140

US Classification:

307530

Abstract:

A sense amplifier (124) for use in determining the binary state of a selected storage device (4) in a semiconductor memory array (2) is disclosed. The sense amplifier (124) comprises a sensing section (150), a reference signal generator (148), and an inverting amplifier section (152). A relatively small current transistor (164) connected between a source of operating potential (158) and a voltage node (162) in the sensing section (150) supplies read currents to the selected storage device (4) via an enabled bit line (8) in the array (2). A second transistor (168) of relatively large size connected to the voltage node (162) in parallel with the current transistor (164) operates to rapidly raise the potential on the bit line (8) when the bit line (8) is first enabled. A third transistor (166) also of relatively large size connected between the voltage node (162) and the bit line (8) serves as a transfer gate for read currents. The reference signal generator (148) feeds a reference potential V. sub.

US Patent:

39381080, Feb 10, 1976

Filed:

Feb 3, 1975

Appl. No.:

5/546546

Inventors:

Phillip J. Salsbury - Sunnyvale CA
George Perlegos - Santa Clara CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G11C 1140
H03K 500
H03K 326
H03K 3353

US Classification:

340173R

Abstract:

A TTL compatible erasable programmable read-only memory (PROM) which uses a single n-channel device having a floating gate for each memory cell. The entire memory including the periphery circuits, are disposed on a silicon substrate. Only a single externally generated high voltage input or "pin" is required for programming.

US Patent:

42648289, Apr 28, 1981

Filed:

Nov 27, 1978

Appl. No.:

5/963973

Inventors:

George Perlegos - Cupertino CA
Saroj Pathak - Campbell CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H03K 19094
H03K 19017
G11C 800

US Classification:

307463

Abstract:

A metal-oxide-semiconductor (MOS) static decoding circuit for selecting an addressed line in a high density memory array, or the like, is disclosed. The circuit may be laid-out along array lines where the lines have a pitch of approximately 12. 25 microns. Three levels of decoding are employed. The highest level permits the pulling-up of a common node in the second level decoder. The third level of decoding selects one of a plurality of array lines coupled to this node. Zero threshold voltage MOS devices are employed for coupling the first and third decoders to the second decoder.

US Patent:

40940128, Jun 6, 1978

Filed:

Oct 1, 1976

Appl. No.:

5/728789

Inventors:

George Perlegos - Santa Clara CA
Phillip J. Salsbury - Sunnyvale CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G11C 1140
G11C 700

US Classification:

365226

Abstract:

A programmable and erasable MOS read-only memory employing floating gate memory cells. Unique, compact decoders allow the high voltage programming signal to be fully decoded without exposing the decoding transistors to the high voltage. The memory employs field-effect transistors having four different voltage thresholds. One such device is employed in the sense amplifiers to provide compensation for process variations and another device is used to allow the output buffers to be readily "powered-down".

US Patent:

44123108, Oct 25, 1983

Filed:

Oct 14, 1980

Appl. No.:

6/196838

Inventors:

George J. Korsh - Redwood City CA
Mark A. Holler - Milpitas CA
George Perlegos - Fremont CA
Paolo Gargini - Palo Alto CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G11C 1140

US Classification:

365185

Abstract:

An improved floating gate MOS EPROM cell which is programmable at a lower potential (12 volts) than prior art devices which often require 25 volts. The oxide thickness between the floating gate and overlying control gate is thicker at the edges of the floating gate than in the central portion. The thicker oxide at the edges prevents uncontrolled DC erasing. This allows a thinner oxide to be used in the central portion and provides the increased capacitance coupling needed for programming at a lower potential.

US Patent:

45198497, May 28, 1985

Filed:

Jul 22, 1983

Appl. No.:

6/515990

Inventors:

George J. Korsh - Redwood City CA
Mark A. Holler - Milpitas CA
George Perlegos - Cupertino CA
Paolo Gargini - Palo Alto CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 2122
H01L 2126

US Classification:

148 15

Abstract:

An improved floating gate MOS EPROM cell which is programmable at a lower potential (12 volts) than prior art devices which often require 25 volts. The oxide thickness between the floating gate and overlying control gate is thicker at the edges of the floating gate than in the central portion. The thicker oxide at the edges prevents uncontrolled DC erasing. This allows a thinner oxide to be used in the central portion and provides the increased capacitance coupling needed for programming at a lower potential.