George E Sery

US Patent:

6414358, Jul 2, 2002

Filed:

Sep 28, 2001

Appl. No.:

09/964616

Inventors:

Wallace W. Lin - San Jose CA
George E. Sery - San Francisco CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 2362

US Classification:

257356, 257360, 257487

Abstract:

Arrangements to reduce charging damage in structures of integrated circuits (ICs).

US Patent:

6566716, May 20, 2003

Filed:

Sep 28, 2001

Appl. No.:

09/964704

Inventors:

Wallace W. Lin - San Jose CA
George E. Sery - San Francisco CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 2976

US Classification:

257355, 257288, 257328, 257356, 257360, 257367

Abstract:

Arrangements to reduce charging damage in structures of integrated circuits (ICs).

US Patent:

6624480, Sep 23, 2003

Filed:

Sep 28, 2001

Appl. No.:

09/964618

Inventors:

Wallace W. Lin - San Jose CA
George E. Sery - San Francisco CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 218234

US Classification:

257355, 257367

Abstract:

Arrangements to reduce charging damage in structures of integrated circuits (ICs).

US Patent:

6960784, Nov 1, 2005

Filed:

Jun 18, 2003

Appl. No.:

10/465741

Inventors:

Wallace W. Lin - San Jose CA, US
George E. Sery - San Francisco CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L023/58

US Classification:

257 48, 257288, 257356, 257360

Abstract:

A charging sensor is provided to detect charging signal during the manufacturing process of integrated circuits and various semiconductor devices. In one embodiment, the charging sensor includes a charging-sensitive insulator layer and complementary elements designed to effectively provide an indicative potential drop across the charging sensitive insulator.

US Patent:

61276960, Oct 3, 2000

Filed:

Jul 2, 1993

Appl. No.:

8/087140

Inventors:

George E. Sery - San Francisco CA
Jan A. Smudski - San Jose CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 2978
H01L 3300

US Classification:

257207

Abstract:

High voltage MOS transistors are fabricated contemporaneously with scaled flash EEPROM array transistors. Active silicon regions separated by field oxide isolation structures are formed as in the prior art. A sacrificial thermal oxide layer simultaneously removes Kooi effect residual nitridization and provides gate oxide for the high voltage transistors of a thickness commensurate with the high voltage application. The sacrificial oxide is thereafter removed from all circuit areas except over high voltage device active areas. Growth of tunnel oxide, first polysilicon, interpoly dielectric, peripheral gate oxide and second polysilicon layers as well as patterning of the layers are accomplished in a known manner. The second polysilicon layer is patterned to create lines which lie within lines formed of the first polysilicon layer, the second polysilicon layer aiding controlling the final channel length of the high voltage devices. A uni-sided lightly doped drain structure is created in n-channel enhancement and intrinsic high voltage devices only by an appropriately shaped mask to block the n+ source-drain implant over a previously implanted tip region disposed between the gate and drain, thereby minimizing hot-carrier effects in the drains.

US Patent:

55808077, Dec 3, 1996

Filed:

Jul 1, 1993

Appl. No.:

8/086140

Inventors:

George E. Sery - San Francisco CA
Jan A. Smudski - San Jose CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 218247

US Classification:

437 47

Abstract:

High voltage MOS transistors are fabricated contemporaneously with scaled flash EEPROM array transistors. Active silicon regions separated by field oxide isolation structures are formed as in the prior art. A sacrificial thermal oxide layer simultaneously removes Kooi effect residual nitridization and provides gate oxide for the high voltage transistors of a thickness commensurate with the high voltage application. The sacrificial oxide is thereafter removed from all circuit areas except over high voltage device active areas. Growth of tunnel oxide, first polysilicon, interpoly dielectric, peripheral gate oxide and second polysilicon layers as well as patterning of the layers are accomplished in a known manner. The second polysilicon layer is patterned to create lines which lie within lines formed of the first polysilicon layer, the second polysilicon layer aiding controlling the final channel length of the high voltage devices. A uni-sided lightly doped drain structure is created in n-channel enhancement and intrinsic high voltage devices only by an appropriately shaped mask to block the n+ source-drain implant over a previously implanted tip region disposed between the gate and drain, thereby minimizing hot-carrier effects in the drains.

US Patent:

56680341, Sep 16, 1997

Filed:

May 14, 1996

Appl. No.:

8/645691

Inventors:

George E. Sery - San Francisco CA
Jan A. Smudski - San Jose CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 218247

US Classification:

438266

Abstract:

High voltage MOS transistors are fabricated contemporaneously with scaled flash EEPROM array transistors. Active silicon regions separated by field oxide isolation structures are formed as in the prior art. A sacrificial thermal oxide layer simultaneously removes Kooi effect residual nitridization and provides gate oxide for the high voltage transistors of a thickness commensurate with the high voltage application. The sacrificial oxide is thereafter removed from all circuit areas except over high voltage device active areas. Growth of tunnel oxide, first polysilicon, interpoly dielectric, peripheral gate oxide and second polysilicon layers as well as patterning of the layers are accomplished in a known manner. The second polysilicon layer is patterned to create lines which lie within lines formed of the first polysilicon layer, the second polysilicon layer aiding controlling the final channel length of the high voltage devices. A uni-sided lightly doped drain structure is created in n-channel enhancement and intrinsic high voltage devices only by an appropriately shaped mask to block the n+ source-drain implant over a previously implanted tip region disposed between the gate and drain, thereby minimizing hot-carrier effects in the drains.