George O Walker

US Patent:

6334247, Jan 1, 2002

Filed:

Jun 11, 1997

Appl. No.:

08/872519

Inventors:

Brian Samuel Beaman - Hyde Park NY
Keith Edward Fogel - Bardonia NY
Paul Alfred Lauro - Nanuet NY
Maurice Heathcote Norcott - Valley Cottage NY
Da-Yuan Shih - Poughkeepsie NY
George Frederick Walker - New York NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01R 4300

US Classification:

29842, 29830, 29843, 174261, 361772

Abstract:

The present invention is directed to a high density test probe which provides a means for testing a high density and high performance integrated circuits in wafer form or as discrete chips. The test probe is formed from a dense array of elongated electrical conductors which are embedded in an compliant or high modulus elastomeric material. A standard packaging substrate, such as a ceramic integrated circuit chip packaging substrate is used to provide a space transformer. Wires are bonded to an array of contact pads on the surface of the space transformer. The space transformer formed from a multilayer integrated circuit chip packaging substrate. The wires are as dense as the contact location array. A mold is disposed surrounding the array of outwardly projecting wires. A liquid elastomer is disposed in the mold to fill the spaces between the wires.

US Patent:

6335104, Jan 1, 2002

Filed:

Feb 22, 2000

Appl. No.:

09/510996

Inventors:

Carlos J. Sambucetti - Croton Hudson NY
Daniel C. Edelstein - New Rochelle NY
John G. Gaudiello - Poughkeepsie NY
Judith M. Rubino - Ossining NY
George Walker - New York NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

B32B 1500

US Classification:

428615, 427125, 427437, 427438, 428637, 428641, 428655, 428656, 428670, 428672, 428673, 428674, 428675, 428680, 428686, 428926, 428936

Abstract:

A method for preparing a copper pad surface for electrical connection that has superior diffusion barrier and adhesion properties is provided. In the method, a copper pad surface is first provided that has been cleaned by an acid solution, a protection layer of a phosphorus or boron-containing metal alloy is then deposited on the copper pad surface, and then an adhesion layer of a noble metal is deposited on top of the protection layer. The protection layer may be a single layer, or two or more layers intimately joined together formed of a phosphorus or boron-containing metal alloy such as Ni-P, Co-P, Co-W-P, Co-Sn-P, Ni-W-P, Co-B, Ni-B, Co-Sn-B, Co-W-B and Ni-W-B to a thickness between about 1,000 and about 10,000. The adhesion layer can be formed of a noble metal such as Au, Pt, Pd and Ag to a thickness between about 500 and about 4,000.

US Patent:

6339024, Jan 15, 2002

Filed:

Jun 28, 2000

Appl. No.:

09/605728

Inventors:

Kevin S. Petrarca - Newburgh NY
Judith M. Rubino - Ossining NY
Carlos J. Sambucetti - Croton on Hudson NY
Richard P. Volant - New Fairfield CT
George F. Walker - New York NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2044

US Classification:

438686, 438238, 438610, 438615, 257200, 257270

Abstract:

A method of manufacturing integrated circuits wherein a conductive structure in a topmost semiconductive layer of an integrated circuit is provided having a thickness greater than or equal to 1. 5 m. The thickness of the conductive structure is sufficiently great as to effectively protect any layers beneath the topmost semiconductive layer from damage from pressure, such as pressure applied by testing probes. In a preferred embodiment, traditional aluminum TD leveling is discarded in favor of gold deposited upon the thickened conductive layer.

US Patent:

6351134, Feb 26, 2002

Filed:

May 7, 1999

Appl. No.:

09/307394

Inventors:

James Marc Leas - South Burlington VT
Robert William Koss - Burlington VT
Jody John Van Horn - Underhill VT
George Frederick Walker - New York NY
Charles Hampton Perry - Poughkeepsie NY
David Lewis Gardell - Fairfax VT
Steve Leo Dingle - Jericho VT
Ronald Prilik - Chesterfield VA

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G01R 3128

US Classification:

324765, 324754

Abstract:

An apparatus and a method for simultaneously testing or burning in all the integrated circuit chips on a product wafer. The apparatus comprises a glass ceramic carrier having test chips and means for connection to pads of a large number of chips on a product wafer. Voltage regulators on the test chips provide an interface between a power supply and power pads on the product chips, at least one voltage regulator for each product chip. The voltage regulators provide a specified Vdd voltage to the product chips, whereby the Vdd voltage is substantially independent of current drawn by the product chips. The voltage regulators or other electronic means limit current to any product chip if it has a short. The voltage regulator circuit may be gated and variable and it may have sensor lines extending to the product chip. The test chips can also provide test functions such as test patterns and registers for storing test results.

US Patent:

6362557, Mar 26, 2002

Filed:

Aug 28, 2000

Appl. No.:

09/649486

Inventors:

Peter A. Gruber - Mohegan Lake NY
Frederic Maurer - Valhalla NY
George F. Walker - New York NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 4108

US Classification:

31032302, 31032316

Abstract:

An actuator scaled to macroscopic or microscopic sizes, uses ultrasonic energy to induce motion of an object in a desired direction. The actuator includes one or more pair of piezoelectric transducers connected with a transducer tip. Supplying the piezoelectric transducers with alternating current electrical power causes the tip to vibrate at ultrasonic frequencies. Urging the vibrating tip into contact with a surface on the object at a selected angle of inclination induces the object to move in the desired direction at a rate determined by the inclination angle. Multiple actuators can be used to induce a fall range of movements of variously shaped objects. In microscopic form, the actuator can be used to create a MEMS device. The optional application of a compliant material either on the transducer tip or on the objects surface enhances the movement induced by the actuator.

US Patent:

6414509, Jul 2, 2002

Filed:

May 3, 2000

Appl. No.:

09/564652

Inventors:

Anilkumar Chinuprasad Bhatt - Johnson City NY
Leo Raymond Buda - Vestal NY
Robert Douglas Edwards - Binghamton NY
Paul Joseph Hart - Endicott NY
Anthony Paul Ingraham - Endicott NY
Voya Rista Markovich - Endwell NY
Jaynal Abedin Molla - Endicott NY
Richard Gerald Murphy - Binghamton NY
George Frederick Walker - New York NY
Bette Jaye Whalen - Vestal NY
Richard Stuart Zarr - Apalachin NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G01R 3102

US Classification:

324765, 324760, 324754

Abstract:

A method of testing semiconductor chips is disclosed. The individual semiconductor chips have I/O, power, and ground contacts. In the method of the invention a chip carrier is provided. The chip carrier has contacts corresponding to the contacts on the semiconductor chip. The carrier contacts have dendritic surfaces. The chip contacts are brought into conductive contact with the conductor pads on the chip carrier. Test signal input vectors are applied to the inputs of the semiconductor chip, and output signal vectors are recovered from the semiconductor chip. After testing, the chip may be removed from the substrate. Alternatively, the chip may be bonded through the dendritic conductor pads to the substrate after successful testing.

US Patent:

6534863, Mar 18, 2003

Filed:

Feb 9, 2001

Appl. No.:

09/781121

Inventors:

George F. Walker - New York NY
Ronald D. Goldblatt - Yorktown Heights NY
Peter A. Gruber - Mohegan Lake NY
Raymond R. Horton - Dover Plains NY
Kevin S. Petrarca - Newburgh NY
Richard P. Volant - New Fairfield CT
Tien-Jen Cheng - Bedford NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2348

US Classification:

257737, 257751, 257761, 257762, 257766, 257769, 257781, 257784

Abstract:

A process is described for forming a common input-output (I/O) site that is suitable for both wire-bond and solder bump flip chip connections, such as controlled-collapse chip connections (C4). The present invention is particularly suited to semiconductor chips that use copper as the interconnection material, in which the soft dielectrics used in manufacturing such chips are susceptible to damage due to bonding forces. The present invention reduces the risk of damage by providing site having a noble metal on the top surface of the pad, while providing a diffusion barrier to maintain the high conductivity of the metal interconnects. Process steps for forming an I/O site within a substrate are reduced by providing a method for selectively depositing metal layers in a feature formed in the substrate. Since the I/O sites of the present invention may be used for either wire-bond or solder bump connections, this provides increased flexibility for chip interconnection options, while also reducing process costs.

US Patent:

6551931, Apr 22, 2003

Filed:

Nov 7, 2000

Appl. No.:

09/706820

Inventors:

Daniel C. Edelstein - White Plains NY
Sung Kwon Kang - Chappaqua NY
Maurice McGlashan-Powell - Yorktown Heights NY
Eugene J. OSullivan - Nyack NY
George F. Walker - New York NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2144

US Classification:

438687, 438678, 438679

Abstract:

A method to selectively cap interconnects with indium or tin bronzes and copper oxides thereof is provided. The invention also provides the interconnect and copper surfaces so formed.