Gerald M Gibson

US Patent:

6680542, Jan 20, 2004

Filed:

May 18, 2000

Appl. No.:

09/575214

Inventors:

Gerald W. Gibson - Orlando FL
Richard W. Gregor - Winter Park FL
Chun-Yung Sung - Orlando FL
Daniel J. Vitkavage - Winter Garden FL
Allen Yen - Orlando FL

Assignee:

Agere Systems Inc. - Allentown PA

International Classification:

H01L 2348

US Classification:

257774, 257758, 257532

Abstract:

The present invention provides a semiconductor device, including an interconnect and a capacitor, and a method of fabrication therefor. The method includes forming a damascene interconnect structure through an interlevel dielectric layer and a dielectric etch stop layer located under the interlevel dielectric, wherein the damascene interconnect structure contacts a first interconnect structure. The method further includes forming a metal-oxide-metal (MOM) capacitor damascene structure through the interlevel dielectric layer and terminating on the dielectric etch stop layer. The damascene structures, may in an alternative embodiment, be dual damascene structures. Furthermore, the damascene interconnect structure and the MOM capacitor may, in another embodiment, make up part of a larger integrated circuit.

US Patent:

6798043, Sep 28, 2004

Filed:

Jan 2, 2002

Appl. No.:

10/038352

Inventors:

Kurt G. Steiner - Orlando FL
Susan Vitkavage - Orlando FL
Steve Lytle - Orlando FL
Gerald Gibson - Orlando FL
Scott Jessen - Orlando FL

Assignee:

Agere Systems, Inc. - Allentown PA

International Classification:

H01L 2358

US Classification:

257637, 257642, 257760

Abstract:

A film structure includes low-k dielectric films and NâH base source films such as barrier layer films, etch-stop films and hardmask films. Interposed between the low-k dielectric film and adjacent NâH base film is a TEOS oxide film which suppresses the diffusion of amines or other NâH bases from the NâH base source film to the low-k dielectric film. The film structure may be patterned using DUV lithography and a chemically amplified photoresist since there are no base groups present in the low-k dielectric films to neutralize the acid catalysts in the chemically amplified photoresist.

US Patent:

20030003765, Jan 2, 2003

Filed:

Jan 2, 2002

Appl. No.:

10/038371

Inventors:

Gerald Gibson - Orlando FL, US
Scott Jessen - Orlando FL, US
Steven Lytle - Orlando FL, US
Kurt Steiner - Orlando FL, US
Susan Vitkavage - Orlando FL, US

International Classification:

H01L023/48

US Classification:

438/760000, 257/760000

Abstract:

A split barrier layer enables copper interconnect wires to be used in conjunction with low-k dielectric films by preventing the diffusion of N—H base groups into photoresists where they can render the photoresist insoluble. The split barrier layer is disposed between the copper and the low-k dielectric and includes a nitrogen-containing, oxygen-free film which contacts the copper, and an oxygen-containing, nitrogen-free film which contacts the low-k dielectric film. The nitrogen-containing film prevents the formation of undesirable copper oxides, and the oxygen-containing film prevents the diffusion of N—H base groups into the low-k dielectric films. The oxygen-containing film may be an oxygen-doped silicon carbide film in an exemplary embodiment. In another embodiment, a film stack of low-k dielectric films includes an etch-stop layer and hardmask each formed of oxygen-doped silicon carbide. The hardmask and etch-stop layer enable the formation of a dual-damascene opening in the film stack, and the film structure of the present invention precludes N—H base groups from diffusing from the low-k dielectric films and neutralizing acid catalysts in the photoresist used to define the dual damascene opening.

US Patent:

20050070112, Mar 31, 2005

Filed:

Sep 30, 2003

Appl. No.:

10/675259

Inventors:

Mario Pita - Winter Springs FL, US
Milton Beachy - Kissimmee FL, US
Gerald Gibson - Danbury CT, US

International Classification:

H01L021/311

US Classification:

438700000

Abstract:

A method for forming a trench in a semiconductor silicon substrate. An anti-reflective coating layer and a photoresist layer are formed over the substrate and patterned in accordance with a location for the trench. During the trench etch into the silicon substrate, the etch environment is monitored to detect the material of the anti-reflective coating layer. The etch process is controlled in response to detecting the removal of this material and the known etch rate differential between the anti-reflective coating material layer and the silicon substrate.