Gerald Michael Johnson

US Patent:

6504395, Jan 7, 2003

Filed:

Aug 30, 2001

Appl. No.:

09/943275

Inventors:

Gerald H. Johnson - Andover MN

Assignee:

Teradyne, Inc. - Boston MA

International Classification:

G01R 3126

US Classification:

324765, 324763, 324771

Abstract:

A power supply circuit is disclosed for use with a semiconductor tester to power a device-under-test. The power supply includes power generation circuitry disposed in the tester to generate power for the device-under-test. Load circuitry is disposed within the tester and coupled to the power generation circuitry to selectively simulate the electrical loading of a device-under-test on the power supply.

US Patent:

6556034, Apr 29, 2003

Filed:

Nov 22, 2000

Appl. No.:

09/718808

Inventors:

Gerald H. Johnson - Andover MN
Michael F. Taylor - Minneapolis MN

Assignee:

Teradyne, Inc. - Boston MA

International Classification:

G01R 3126

US Classification:

324765, 3241581

Abstract:

A power supply is disclosed for use with a device-under-test disposed on a device board. The power supply includes a high-accuracy remote supply circuit including respective force and sense lines and a high-speed local supply circuit. The local supply circuit includes an active boost circuit having respective boost and sense lines coupled to the force and sense lines. The active boost circuit is operative to selectively cooperate with the remote supply circuit and, when the device-under-test demands a large dynamic current, provide the dynamic current until the remote supply circuit responds to the current demand.

US Patent:

6756807, Jun 29, 2004

Filed:

Nov 30, 2001

Appl. No.:

10/006523

Inventors:

Gerald H. Johnson - Andover MN
Michael F. Taylor - Minneapolis MN

Assignee:

Teradyne, Inc. - Boston MA

International Classification:

G01R 3136

US Classification:

324771

Abstract:

A modular power supply architecture for automatic test equipment is disclosed. The power supply architecture includes a control module having a control signal output line and a plurality of output modules. The control module includes control circuitry to generate a control signal along the control signal output line and measurement circuitry coupled to the control signal output line. The output modules have respective control inputs coupled in parallel to the control signal output line to receive the control signal and respective current outputs connected in parallel. The output modules are operative in response to the control signal to generate respective currents at the current outputs. A current output bus receives and sums the respective current outputs, the output bus being isolated from the control signal line.

US Patent:

6906578, Jun 14, 2005

Filed:

Oct 30, 2001

Appl. No.:

10/000440

Inventors:

Gerald H. Johnson - Andover MN, US

Assignee:

Teradyne, Inc. - Boston MA

International Classification:

G05F001/10
G05F003/02

US Classification:

327538

Abstract:

A control loop circuit is disclosed for optimizing a power supply output under varying load conditions. The power supplye has a main loop amplifier and an output stage to generate the output. The control loop circuit includes a static control path coupled to the output and having an error amplifier. The error amplifier is operative to generate an error signal for presentation to the main loop amplifier where the error signal represents the difference between a desired output and a sensed output. A dynamic control path is coupled to the error amplifier output and is responsive to the error signal to generate a dynamic compensation signal. The dynamic control path has an output coupled to the main loop amplifier output.

US Patent:

7085668, Aug 1, 2006

Filed:

Aug 20, 2004

Appl. No.:

10/923488

Inventors:

Gerald H. Johnson - Andover MN, US

Assignee:

Teradyne, Inc. - Boston MA

International Classification:

G04F 1/00

US Classification:

702117, 702 72, 702 78, 702176, 714700

Abstract:

A time measurement circuit includes N time stamping units that each includes a dual sinusoid interpolator for achieving high timing resolution. The time measurement circuit is capable of time stamping input signals at a high re-trigger rate, and is thus well suited for quickly measuring the timing jitter of test signals in automatic test systems.

US Patent:

8373432, Feb 12, 2013

Filed:

Mar 16, 2010

Appl. No.:

12/724727

Inventors:

Gerald H. Johnson - Andover MN, US

Assignee:

Teradyne Inc. - North Reading MA

International Classification:

G01R 31/00
G01R 31/20
G01R 31/02

US Classification:

32475605, 32475407, 32476201

Abstract:

Automated test equipment for high-speed testing of devices under test (DUTs) includes a tester channel circuit generating a high-speed electrical test signal applied to the signal input terminal of each DUT, and a contacter board in physical and electrical contact with the DUTs. The contacter board has a high-speed signal transmission channel including (1) an electrical contact at which the high-speed electrical test signal is received, (2) conductive etch extending from the electrical contact to isolation areas each adjacent to the signal input terminal of a respective DUT, and (3) an embedded series isolation resistor formed on an inner layer of the contacter board at a respective isolation area forming a connection between the conductive etch and the adjacent signal input terminal of the respective DUT.

US Patent:

20040149867, Aug 5, 2004

Filed:

Aug 9, 2002

Appl. No.:

10/214508

Inventors:

Gerald Johnson - Long Lake MN, US

International Classification:

A47G023/02

US Classification:

248/146000

Abstract:

A bow and arrow bolder () having a base (); an upright (); and a bow bracket () capable of holding at least one bow on each side of the upright (). A preferred holder () is fabricated from PVC pipe and fittings, with the base () including end caps () that can be removed to add ballast (e.g., sand) to increase stability. Upright () is preferably removably attached to the base (), and preferably forms or carries at least two “sleeves” for holding at least two sets of arrows. Each bow bracket () preferably includes two pairs of cantilevered “keepers” () that extend laterally outwardly from the upright (), and the keepers () are tilted in such a way that the bow(s) can be held in a substantially vertical, ready position.

US Patent:

45462690, Oct 8, 1985

Filed:

Dec 1, 1983

Appl. No.:

6/557024

Inventors:

Gerald H. Johnson - White Bear Lake MN

Assignee:

Control Data Corporation - Minneapolis MN

International Classification:

H03K 513

US Classification:

307269

Abstract:

In a first searching mode of the control program for the microprocessor, the microprocessor starts with a selected clock input and associated delay circuit and sets the delay circuit to an initial clocking point which is intermediate to the minimum and maximum delay points. The microprocessor then, at each pass of the control program, successively increments the delay period interposed by the delay circuit to cause the clock pulse to arrive later and later in time at the clock input until the associated circuit fails, to indicate the late clocking failure limit. In the second searching mode of the microprocessor control program, the microprocessor starts at the late clocking failure limit and at each subsequent pass of the program successively decrements the delay period interposed by the delay circuit to cause the clock signal to arrive earlier and earlier in time until the semiconductor device fails again, to indicate the early clocking failure limit. The early clocking failure limit and the late clocking failure limit together define the clocking window for the semiconductor device. The microprocessor sets the delay circuit to the mid-point of the clocking window which is the optimal clocking point for the particular clock input.