Gerald F Luiz from 151 Anne Way, Los Gatos, CA 95032, age 55, Phone: 6509880565

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Automatic Dependent Task Launch
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US Patent:

20130198760, Aug 1, 2013
Filed:

Jan 27, 2012
Appl. No.:

13/360581
Inventors:

Philip Alexander CUADRA - San Francisco CA, US
Lacky V. Shah - Los Altos Hills CA, US
Timothy John Purcell - Provo UT, US
Gerald F. Luiz - Los Gatos CA, US
International Classification:

G06F 9/46
US Classification:

718106
Abstract:

One embodiment of the present invention sets forth a technique for automatic launching of a dependent task when execution of a first task completes. Automatically launching the dependent task reduces the latency incurred during the transition from the first task to the dependent task. Information associated with the dependent task is encoded as part of the metadata for the first task. When execution of the first task completes a task scheduling unit is notified and the dependent task is launched without requiring any release or acquisition of a semaphore. The information associated with the dependent task includes an enable flag and a pointer to the dependent task. Once the dependent task is launched, the first task is marked as complete so that memory storing the metadata for the first task may be reused to store metadata for a new task.

Compute Work Distribution Reference Counters
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US Patent:

20130117758, May 9, 2013
Filed:

Nov 8, 2011
Appl. No.:

13/291369
Inventors:

Philip Alexander Cuadra - Mountain View CA, US
Karim M. Abdalla - Menlo Park CA, US
Luke Durant - Santa Clara CA, US
Gerald F. Luiz - Los Gatos CA, US
Timothy John Purcell - Provo UT, US
Lacky V. Shah - Los Altos Hills CA, US
International Classification:

G06F 9/46
US Classification:

718104
Abstract:

One embodiment of the present invention sets forth a technique for managing the allocation and release of resources during multi-threaded program execution. Programmable reference counters are initialized to values that limit the amount of resources for allocation to tasks that share the same reference counter. Resource parameters are specified for each task to define the amount of resources allocated for consumption by each array of execution threads that is launched to execute the task. The resource parameters also specify the behavior of the array for acquiring and releasing resources. Finally, during execution of each thread in the array, an exit instruction may be configured to override the release of the resources that were allocated to the array. The resources may then be retained for use by a child task that is generated during execution of a thread.

System, Method And Computer Program Product For Implementing Anti-Aliasing Operations Using A Programmable Sample Pattern Table
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US Patent:

20170061680, Mar 2, 2017
Filed:

Sep 6, 2016
Appl. No.:

15/257650
Inventors:

- Santa Clara CA, US
Jeffrey Alan Bolz - Austin TX, US
Timothy Paul Lottes - Cary NC, US
Rui Manuel Bastos - Porto Alegre, BR
Barry Nolan Rodgers - Madison AL, US
Gerald F. Luiz - Los Gatos CA, US
International Classification:

G06T 15/50
G06T 15/40
G06T 15/00
G06T 15/04
Abstract:

A system, method, and computer program product are provided for implementing anti-aliasing operations using a programmable sample pattern table. The method includes the steps of receiving an instruction that causes one or more values to be stored in one or more corresponding entries of the programmable sample pattern table and performing an anti-aliasing operation based on at least one value stored in the programmable sample pattern table. At least one value is selected from the programmable sample pattern table based on, at least in part, a location of one or more corresponding pixels.

System, Method, And Computer Program Product For Implementing Anti-Aliasing Operations Using A Programmable Sample Pattern Table
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US Patent:

20150138228, May 21, 2015
Filed:

Nov 15, 2013
Appl. No.:

14/082038
Inventors:

- Santa Clara CA, US
Jeffrey Alan Bolz - Austin TX, US
Timothy Paul Lottes - Cary NC, US
Rui Manuel Bastos - Porto Alegre, BR
Barry Nolan Rodgers - Madison AL, US
Gerald F. Luiz - Los Gatos CA, US
Assignee:

NVIDIA Corporation - Santa Clara CA
International Classification:

G06T 5/00
G06T 1/20
US Classification:

345611
Abstract:

A system, method, and computer program product are provided for implementing anti-aliasing operations using a programmable sample pattern table. The method includes the steps of receiving an instruction that causes one or more values to be stored in one or more corresponding entries of the programmable sample pattern table and performing an anti-aliasing operation based on at least one value stored in the programmable sample pattern table. At least one value is selected from the programmable sample pattern table based on, at least in part, a location of one or more corresponding pixels.

Interleaved Instruction Debugger
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US Patent:

20140344556, Nov 20, 2014
Filed:

May 15, 2013
Appl. No.:

13/895266
Inventors:

- Santa Clara CA, US
Arthur DANSKIN - Los Angeles CA, US
Gerald LUIZ - Los Gatos CA, US
Assignee:

NVIDIA Corporation - Santa Clara CA
International Classification:

G06F 9/30
US Classification:

712227
Abstract:

One or more embodiments of the invention are directed to a method including monitoring execution of a set of programs each including a set of instructions executing interleaved with other instructions of the set of instructions, where each of the set of instructions includes at least one operation operating on a set of threads; organizing a first set of instructions corresponding to a first program of the set of programs based on an execution order of the first set of instructions; generating a result set representing the first set of instructions organized based on the execution order; and displaying the result set.

Technique For Saving And Restoring Thread Group Operating State
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US Patent:

20140165072, Jun 12, 2014
Filed:

Dec 11, 2012
Appl. No.:

13/711093
Inventors:

- Santa Clara CA, US
Lacky V. SHAH - Los Altos Hills CA, US
Gerald F. LUIZ - Los Gatos CA, US
Philip Alexander CUADRA - San Francisco CA, US
Luke DURANT - Santa Clara CA, US
Shirish GADRE - Fremont CA, US
Assignee:

NVIDIA CORPORATION - Santa Clara CA
International Classification:

G06F 9/50
US Classification:

718104
Abstract:

A streaming multiprocessor (SM) included within a parallel processing unit (PPU) is configured to suspend a thread group executing on the SM and to save the operating state of the suspended thread group. A load-store unit (LSU) within the SM re-maps local memory associated with the thread group to a location in global memory. Subsequently, the SM may re-launch the suspended thread group. The LSU may then perform local memory access operations on behalf of the re-launched thread group with the re-mapped local memory that resides in global memory.