Gerald W Reynolds

US Patent:

60783362, Jun 20, 2000

Filed:

May 12, 1998

Appl. No.:

9/076380

Inventors:

Gerald W. Reynolds - Fort Collins CO

Assignee:

Hewlett-Packard Company - Palo Alto CA

International Classification:

G09G 500
G06F 1316

US Classification:

345513

Abstract:

The present invention provides a graphics memory system comprising at least one memory controller that utilizes a first-in-first-out (FIFO) memory architecture in combination with a look-head paging technique for paging a frame buffer memory having a multi-bank architecture. The memory controller controls accessing of a frame buffer memory of the graphics memory system. The frame buffer memory comprises a multi-bank architecture, which preferably is a two-bank architecture. The FIFO architecture comprises a plurality of FIFO memory devices (FIFOs). The memory controller is capable of determining whether a particular FIFO contains no more transactions for a particular bank and, if not, of causing that bank to be re-paged for a different FIFO. In this respect, the memory controller performs what is referred to herein as "inter-FIFO" look-ahead paging. Each of the FIFOs preferably comprises intelligence to enable it to perform look-ahead paging within that particular FIFO, or "intra-FIFO" look-ahead paging.