Gerald L Robinson

US Patent:

52427110, Sep 7, 1993

Filed:

Aug 16, 1991

Appl. No.:

7/746458

Inventors:

Jeffrey D. DeNatale - Thousand Oaks CA
John F. Flintoff - Thousand CA
Alan B. Harker - Thousand CA
Patrick J. Hood - Thousand CA
Gerald D. Robinson - Dayton OH

Assignee:

Rockwell International Corp. - Seal Beach CA

International Classification:

C23C 1600

US Classification:

427249

Abstract:

A high temperature resist process is combined with microlithographic patterning for the production of materials, such as diamond films, that require a high temperature deposition environment. A conventional polymeric resist process may be used to deposit a pattern of high temperature resist material. With the high temperature resist in place and the polymeric resist removed, a high temperature deposition process may proceed without degradation of the resist pattern. After a desired film of material has been deposited, the high temperature resist is removed to leave the film in the pattern defined by the resist. For diamond films, a high temperature silicon nitride resist can be used for microlithographic patterning of a silicon substrate to provide a uniform distribution of diamond nucleation sites and to improve diamond film adhesion to the substrate. A fine-grained nucleation geometry, established at the nucleation sites, is maintained as the diamond film is deposited over the entire substrate after the silicon nitride resist is removed. The process can be extended to form microstructures of fine-grained polycrystalline diamond, such as rotatable microgears and surface relief patterns, that have the desirable characteristics of hardness, wear resistance, thermal conductivity, chemical inertness, anti-reflectance, and a low coefficient of friction.

US Patent:

51477408, Sep 15, 1992

Filed:

Aug 9, 1990

Appl. No.:

7/564996

Inventors:

Gerald D. Robinson - Westlake Village CA

Assignee:

Rockwell International Corporation - Seal Beach CA

International Classification:

G03F 900

US Classification:

430 5

Abstract:

A mask and lithographic process is disclosed for the formation of conductive patterns on substrates, particularly in connection with the formation of high electron mobility transistors (HEMT) and metal-semiconductor field effect transistors (MESFET). The technique allows the formation of sub-half micron conductive patterns on semiconductor substrates using optical lithography and a multilayer portable conformable mask. The method includes the application of optical contact lithography to a conventional photoresist followed by a deep UV flood exposure of an underlying multilayer PMGI portion. Metal is deposited on a semiconductor substrate through the mask formed by the photoresist and PMGI layers to produce sub-half micron conductive patterns.