Gerald W Rogers

US Patent:

20140075082, Mar 13, 2014

Filed:

Sep 13, 2012

Appl. No.:

13/615442

Inventors:

James A. Coleman - Mesa AZ, US
Durgesh Srivastava - Santa Clara CA, US
Gerald Rogers - Chandler AZ, US
Scott M. Oehrlein - Chandler AZ, US

International Classification:

G06F 13/20

US Classification:

710316

Abstract:

Apparatuses, methods and storage media associated with integrated circuits (IC) or system-on-chips (SOC) are disclosed herein. In embodiments, a multi-core IC may include a number of central processing units (CPUs), and a number of input/output (I/O) resources. The IC may further include a switch fabric configured to couple the CPUs with the I/O resources, and a register to be selectively configured to exclusively couple one of the CPUs with one of the I/O resources to form a logical domain that computationally isolates the one CPU and the one I/O resource from other CPUs and other I/O. Other embodiments may be described and claimed.

US Patent:

20220197685, Jun 23, 2022

Filed:

Aug 3, 2021

Appl. No.:

17/392861

Inventors:

- Santa Clara CA, US
Gerald Rogers - Chandler AZ, US
Shih-Wei Roger Chien - Shanghai, CN
Namakkal Venkatesan - Portland OR, US
Rajesh Gadiyar - Chandler AZ, US

International Classification:

G06F 9/455
G06F 13/16
G06F 13/40
G06F 13/42
G06F 12/0815
G06F 12/0875
G06F 12/0811
G06F 9/50
G06F 9/38

Abstract:

Technologies for application-specific network acceleration include a computing device including a processor and an accelerator device such as a field-programmable gate array (FPGA). The processor and the accelerator device are coupled via a coherent interconnect and may be included in a multi-chip package. The computing device binds a virtual machine executed by the processor with an application function unit of the accelerator device via the coherent interconnect. The computing device processes network application data with the virtual machine and the application function unit within a coherency domain maintained with the coherent interconnect. Processing the network data may include processing a packet of a network flow by the virtual machine and processing subsequent packets of the network flow by the application function unit. Other embodiments are described and claimed.

US Patent:

20230115114, Apr 13, 2023

Filed:

Dec 9, 2022

Appl. No.:

18/078382

Inventors:

- Santa Clara CA, US
Cunming Liang - Shanghai, CN
Jian Wang - Shanghai, CN
Martin Roberts - High Wycombe, GB
Shih-Wei Chien - Taiwan, CN
Gerald Alan Rogers - Chandler AZ, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H04L 49/00
G06F 12/0868
G06F 12/10
G06F 12/12
H04L 49/90

Abstract:

There is disclosed an example of a computing apparatus for providing a hardware-assisted virtual switch on a host, including: a hardware virtual switch (vSwitch) circuit; and a hardware virtual host (vHost) circuit, the vHost circuit having an interface driver specific to the hardware vSwitch and configured to provide a vHost data plane to: provide a plurality of hardware queues to communicatively couple the hardware vSwitch to a guest virtual function (VF); and present to a virtual network driver of the guest VF an interface that is backward compatible with a software network interface.

US Patent:

20210272467, Sep 2, 2021

Filed:

Sep 28, 2018

Appl. No.:

17/256105

Inventors:

- Santa Clara CA, US
Addicam V. Sanjay - Gilbert AZ, US
Karthik Veeramani - Hillsboro OR, US
Gabriel L. Silva - Phoenix AZ, US
Marcos P. Da Silva - Chandler AZ, US
Jose A. Avalos - Chandler AZ, US
Stephen T. Palermo - Paradise Valley AZ, US
Glen J. Anderson - Beaverton OR, US
Meng Shi - Hillsboro OR, US
Benjamin W. Bair - Hillsboro OR, US
Pete A. Denman - Portland OR, US
Reese L. Bowes - Hillsboro AZ, US
Rebecca A. Chierichetti - Hillsboro OR, US
Ankur Agrawal - Jaipur, IN
Gerald A. Rogers - Chandler AZ, US
Shih-Wei Roger Chien - Kaohsiung City, TW
Lenitra M. Durham - Beaverton OR, US
Giuseppe Raffa - Portland OR, US
Irene Liew - Portland OR, US
Edwin Verplanke - Queen Creek AZ, US

International Classification:

G09B 5/06
G06T 19/00
G06F 9/38
G06F 9/455

Abstract:

In one embodiment, an apparatus comprises a memory and a processor. The memory is to store sensor data, wherein the sensor data is captured by a plurality of sensors within an educational environment. The processor is to: access the sensor data captured by the plurality of sensors; identify a student within the educational environment based on the sensor data; detect a plurality of events associated with the student based on the sensor data, wherein each event is indicative of an attention level of the student within the educational environment; generate a report based on the plurality of events associated with the student; and send the report to a third party associated with the student.

US Patent:

20200403940, Dec 24, 2020

Filed:

Oct 24, 2017

Appl. No.:

16/643626

Inventors:

- Santa Clara CA, US
Cunming LIANG - Shanghai, CN
Jian WANG - Shanghai, CN
Martin ROBERTS - Wargrave, GB
Shih-Wei CHIEN - Kaohsiung City, CN
Gerald Alan ROGERS - Chandler AZ, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H04L 12/931
H04L 12/861
G06F 12/0868
G06F 12/10
G06F 12/12

Abstract:

There is disclosed an example of a computing apparatus for providing a hardware-assisted virtual switch on a host, including: a hardware virtual switch (vSwitch) circuit; and a hardware virtual host (vHost) circuit, the vHost circuit having an interface driver specific to the hardware vSwitch and configured to provide a vHost data plane to: provide a plurality of hardware queues to communicatively couple the hardware vSwitch to a guest virtual function (VF); and present to a virtual network driver of the guest VF an interface that is backward compatible with a software network interface.

US Patent:

20190042292, Feb 7, 2019

Filed:

Feb 25, 2018

Appl. No.:

15/904371

Inventors:

- Sant Clara CA, US
Gerald Rogers - Chandler AZ, US
Shih-Wei Roger Chien - Shanghai, CN
Namakkal Venkatesan - Portland OR, US
Rajesh Gadiyar - Chandler AZ, US

International Classification:

G06F 9/455
G06F 13/40

Abstract:

Technologies for application-specific network acceleration include a computing device including a processor and an accelerator device such as a field-programmable gate array (FPGA). The processor and the accelerator device are coupled via a coherent interconnect and may be included in a multi-chip package. The computing device binds a virtual machine executed by the processor with an application function unit of the accelerator device via the coherent interconnect. The computing device processes network application data with the virtual machine and the application function unit within a coherency domain maintained with the coherent interconnect. Processing the network data may include processing a packet of a network flow by the virtual machine and processing subsequent packets of the network flow by the application function unit. Other embodiments are described and claimed.

US Patent:

20190034363, Jan 31, 2019

Filed:

Dec 22, 2017

Appl. No.:

15/853670

Inventors:

- Santa Clara CA, US
Gerald Rogers - Chandler AZ, US
Shih-Wei Chien - Shanghai, CN
Namakkal Venkatesan - Portland OR, US

International Classification:

G06F 13/16
G06F 9/455
G06F 13/40
G06F 13/42
G06F 12/0811
G06F 12/0815
G06F 12/0875

Abstract:

A computer system may comprise a multi-chip package (MCP), which includes multi-core processor circuitry and hardware accelerator circuitry. The multi-core processor circuitry may comprise a plurality of processing cores, and the hardware accelerator circuitry may be coupled with the multi-core processor circuitry via one or more coherent interconnects and one or more non-coherent interconnects. A coherency domain of the MCP may be extended to encompass the hardware accelerator circuitry, or portions thereof An interconnect selection module may select an individual coherent interconnect or an individual non-coherent interconnect based on application requirements of an application to be executed and a workload characteristic policy. Other embodiments are described and/or claimed.