Gerald Michael Rogers

US Patent:

42491940, Feb 3, 1981

Filed:

Aug 29, 1977

Appl. No.:

5/828359

Inventors:

Gerald D. Rogers - Houston TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 2702
H01L 2978
H01L 2934

US Classification:

357 51

Abstract:

An MOS capacitor for N-channel silicon gate integrated circuits employs a polycrystalline silicon layer as one plate, and a silicon oxide dielectric. The lower plate consists of a region which is implanted by an ion beam to produce a depleted region. This device has a constant capacitance regardless of gate voltage in normal operating logic levels.

US Patent:

39342336, Jan 20, 1976

Filed:

Sep 24, 1973

Appl. No.:

5/400471

Inventors:

Roger J. Fisher - Houston TX
Gerald D. Rogers - Houston TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G11C 1300

US Classification:

340173R

Abstract:

A read-only-memory for use in an electronic calculator or the like, implemented in a large-scale-integrated MOS semiconductor chip. The ROM is designed to save area on the chip by employing a virtual ground feature and conserve power by a precharge system. The memory cells are in an array defining X and Y lines, with the presence or absence of a bit being determined by thin oxide under an X line between adjacent Y lines. Ground lines are provided for groups of Y lines, and the Y-decode matrix includes an arrangement for connecting a selected Y-line to a non-adjacent ground line. Only the X decode section is precharged rather than all the X lines. The entire decode and read out is accomplished in a small part of the instruction cycle of the calculator.

US Patent:

42952646, Oct 20, 1981

Filed:

Nov 15, 1976

Appl. No.:

5/741815

Inventors:

Gerald D. Rogers - Houston TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 744
B01J 1700

US Classification:

29571

Abstract:

An MOS capacitor for N-channel silicon gate integrated circuits employs a polycrystalline silicon layer as one plate, and a silicon oxide dielectric. The lower plate consists of a region which is implanted by an ion beam to produce a depleted region. This device has a constant capacitance regardless of gate voltage in normal operating logic levels.

US Patent:

40598268, Nov 22, 1977

Filed:

Dec 29, 1975

Appl. No.:

5/645173

Inventors:

Gerald D. Rogers - Houston TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G11C 1140
G11C 1700

US Classification:

365104

Abstract:

N-channel silicon gate MOS memory cells are programmed by an ion implant step which is done prior to forming the gates or the diffused source and drain regions. The implanted devices have a threshold voltage which is about zero, so the devices cannot be turned off at usual logic levels. Either ROM or RAM arrays can be made using implant for programming.