Gerald W Swift

US Patent:

6433638, Aug 13, 2002

Filed:

Sep 6, 2000

Appl. No.:

09/655816

Inventors:

Randolph B. Heineke - Rochester MN
Scott Allen Olson - Rochester MN
David Peter Swart - Pine Island MN
Gerald Wayne Swift - Rolling Hills Estates CA

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03F 345

US Classification:

330260, 330 85, 330110, 330311

Abstract:

A fully balanced transimpedance amplifier for high speed and low voltage applications is provided. An input stage of the amplifier uses a matched pair of common source connected transistors with sources tied directly to ground to eliminate the Vds overhead usually found in differential pairs. The ground connection minimizes a source resistance noise component, while matching minimizes power supply noise generation and susceptibility for an array of amplifiers. Feedback resistors along with diode connected MESFETS determine the transimpedance of the amplifier. The nonlinearity of diodes helps to soften clipping. Transresistance also determined the noise generated by the amplifier, and the diode connected MESFETS offer lower noise than resistors for the same impedance. Stability is achieved through use of only a single stage of gain in a loop of the input stage, while additional gain is achieved through cascading in the input stage. A differential stage minimizes any difference in amplitude between two sides of the amplifier input stage.

US Patent:

6594893, Jul 22, 2003

Filed:

Sep 18, 2001

Appl. No.:

09/953934

Inventors:

Mark J. Bailey - Lake City MN
Michael John Shea - Rochester MN
Gerald Wayne Swift - Rolling Hills Estates CA

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H05K 310

US Classification:

29846, 29825, 29852, 174254, 174255, 427 97

Abstract:

A surface laminar circuit board includes an insulating layer, and a signal ground conductive layer disposed on an upper surface of the insulating layer. The conductive layer has a hole formed therein. A photosensitive dielectric layer is disposed on an upper surface of the signal ground conductive layer. The dielectric layer has a photo micro-via formed therein. A signal trace is disposed on the photosensitive dielectric layer, and is electrically coupled with the signal ground conductive layer by way of the photo micro-via. A conductive pad is provided, which has a majority thereof within an area defined by an outer periphery of the hole. The conductive pad is electrically coupled with the signal trace. A surface mounted component is mounted on the conductive pad.

US Patent:

6734369, May 11, 2004

Filed:

Aug 31, 2000

Appl. No.:

09/651334

Inventors:

Mark J. Bailey - Lake City MN
Michael John Shea - Rochester MN
Gerald Wayne Swift - Rolling Hills Estates CA

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H05K 103

US Classification:

174255, 361768, 361794, 361795

Abstract:

A surface laminar circuit board includes an insulating layer, and a signal ground conductive layer disposed on an upper surface of the insulating layer. The conductive layer has a hole formed therein. A photosensitive dielectric layer is disposed on an upper surface of the signal ground conductive layer. The dielectric layer has a photo micro-via formed therein. A signal trace is disposed on the photosensitive dielectric layer, and is electrically coupled with the signal ground conductive layer by way of the photo micro-via. A conductive pad is provided, which has a majority thereof within an area defined by an outer periphery of the hole. The conductive pad is electrically coupled with the signal trace. A surface mounted component is mounted on the conductive pad.

US Patent:

20020131724, Sep 19, 2002

Filed:

Mar 15, 2001

Appl. No.:

09/809127

Inventors:

Mark Bailey - Lake City MN, US
David Gaio - Rochester MN, US
William Hogan - Rochester MN, US
Gerald Swift - Rolling Hills Estates CA, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION

International Classification:

G02B006/42
G02B006/30

US Classification:

385/088000, 385/049000

Abstract:

A high frequency matching method and silicon optical bench employing a high frequency matching network are provided. The silicon optical bench comprises a silicon wafer defining a structure for precisely locating an electro-optical component. A predefined metal trace pattern is formed on a surface of the silicon wafer. The predefined metal trace pattern at least one electrical device, such as a thin film resistor, a capacitor or an inductor; or a selected combination of at least one thin film resistor, capacitor or inductor formed at selected predefined locations within the predefined metal trace pattern. The predefined metal trace pattern provides a high frequency impedance matching network for connection with the electro-optical component. The predefined metal trace pattern includes a plurality of selected widths within the predefined metal trace pattern. The widths are selectively provided for changing inductance within the predefined metal trace pattern. The predefined metal trace pattern includes at least one capacitive stub. The capacitive stub is formed within the predefined metal trace pattern for balancing inductance within the predefined metal trace pattern. The thin film resistor is formed at a predefined location within the predefined metal trace pattern by depositing the thin film resistor on a surface of the predefined metal trace pattern. A pair of thin film resistors can be formed at predefined locations within the predefined metal trace pattern adjacent to a pair of traces of the predefined metal trace pattern that connect to electro-optical component, such as a laser.

US Patent:

60368152, Mar 14, 2000

Filed:

Apr 30, 1998

Appl. No.:

9/070819

Inventors:

Carl W. Peterson - Carson CA
Harry C. Jones - Cerritos CA
Mir Akbar Ali - Lomita CA
Gerald W. Swift - Rolling Hills Estates CA

Assignee:

Hughes Electronics Corporation - El Segundo CA

International Classification:

B32B 3100

US Classification:

156330

Abstract:

A phased array (20) and method for constructing the same are disclosed. The phased array (20) includes a superstructure (22) with cavities (40) therein. A cover plate (28) is mounted to the superstructure (22) and cooperates with the cavities (40) to form cavity style filters therebetween and to form a box-beam type superstructure. Ideally, the superstructure (22) is self supporting. Electronic modules (32) and amplifiers (33) are mounted to the superstructure (22). The method includes machining a block of material to form a webbed superstructure with cavities (40) therein. A cover plate (28) is mounted to the superstructure (22) over the cavities (40) to form cavity style filters. Amplifiers (32) and antenna elements (30) are then affixed to the superstructure (22) and cover plate (28). Ideally, the cover plate (28) is affixed to the superstructure (22) using an electrically conductive adhesive.

US Patent:

47289040, Mar 1, 1988

Filed:

Jan 27, 1987

Appl. No.:

7/009644

Inventors:

Gerald W. Swift - Rolling Hills Estates CA
Patrick J. O'Sullivan - Manhattan Beach CA

Assignee:

TRW Inc. - Redondo Beach CA

International Classification:

H03F 360

US Classification:

330286

Abstract:

A structure for extra-high-frequency circuit modules, to take advantage of the low losses and convenience of assembly of waveguides, and at the same time to take advantage of the ease of tuning of microstrip lines. Each module is adapted to be conveniently connectable to others in a cascade arrangement, and each presents a waveguide interface to adjacent modules. If a module is to contain an active device, such as an amplifier, the module incorporates a microstrip section and two transition sections to couple the microstrip section to the waveguides at input and output. The microstrip section is easily tunable and is easier to couple to the active device.

US Patent:

57811628, Jul 14, 1998

Filed:

Jan 12, 1996

Appl. No.:

8/585825

Inventors:

Carl W. Peterson - Carson CA
Harry C. Jones - Cerritos CA
Mir Akbar Ali - Lomita CA
Gerald W. Swift - Rolling Hills Estates CA

Assignee:

Hughes Electronic Corporation - Los Angeles CA

International Classification:

H01Q 2100

US Classification:

343853

Abstract:

A phased array (20) and method for constructing the same are disclosed. The phased array (20) includes a superstructure (22) with cavities (40) therein. A cover plate (28) is mounted to the superstructure (22) and cooperates with the cavities (40) to form cavity style filters therebetween and to form a box-beam type superstructure. Ideally, the superstructure (22) is self supporting. Electronic modules (32) and amplifiers (33) are mounted to the superstructure (22). The method includes machining a block of material to form a webbed superstructure with cavities (40) therein. A cover plate (28) is mounted to the superstructure (22) over the cavities (40) to form cavity style filters. Amplifiers (32) and antenna elements (30) are then affixed to the superstructure (22) and cover plate (28). Ideally, the cover plate (28) is affixed to the superstructure (22) using an electrically conductive adhesive.

US Patent:

46848746, Aug 4, 1987

Filed:

Feb 5, 1985

Appl. No.:

6/698296

Inventors:

Gerald W. Swift - Rolling Hills Estates CA
David I. Stones - Torrance CA

Assignee:

TRW Inc. - Redondo Beach CA

International Classification:

H01P 512

US Classification:

333125

Abstract:

A microwave radial power divider/combiner device having desirably broad bandwidth response over a selected frequency range. The device includes a radial waveguide that has a number of adjoining annular sections, each of selected radial length and axial height, to provide lumped circuit parameters closely euqivalent to those of an ideal filter with the desired passband characteristics. The ideal filter is first designed using conventional synthesis techniques, then modified, if necessary, to allow its realization in radial waveguide form. The waveguide sections are selected to have lengths and uniform heights to approximate the lumped circuit parameters of the filter, and the dimensions are then optimized to provide the closest approach to the desired performance characteristics.