Gerard V Kopcsay

US Patent:

6342823, Jan 29, 2002

Filed:

Aug 26, 1998

Appl. No.:

09/140643

Inventors:

Allan Harvey Dansky - Poughkeepsie NY
Alina Deutsch - Chappaqua NY
Gerard Vincent Kopcsay - Yorktown Heights NY
Phillip John Restle - Katonah NY
Howard Harold Smith - Beacon NY

Assignee:

International Business Machines Corp. - Armonk NY

International Classification:

H01P 500

US Classification:

333 1, 333 99 R

Abstract:

A method and system for reducing the computation complexity and improving accuracy of delay and crosstalk calculation in transmission-lines with frequency-dependent losses. An analysis tool based on restricted coupled-line topologies, simple two-dimensional to three-dimensional RLC matrix conversion, and use of prestored synthesized circuits that accurately capture frequency-dependent loss effects. The CAD tool can handle frequency-dependent resistive and inductive effects for coupled-interconnections on large microprocessor chips with 10K of critical nets. This is done in an interactive manner during the design cycle and allows first path fast product design.

US Patent:

6418401, Jul 9, 2002

Filed:

Feb 11, 1999

Appl. No.:

09/248667

Inventors:

Allan H. Dansky - Poughkeepsie NY
Alina Deutsch - Chappaqua NY
Gerard V. Kopcsay - Yorktown Heights NY
Phillip J. Restle - Katonah NY
Howard H. Smith - Beacon NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1750

US Classification:

703 27, 703 13, 703 19, 716 4, 716 6

Abstract:

A method for reducing the computation time and improving the productivity in designing high-performance microprocessor chips that have no failuresâdue to crosstalk noise. The technique allows a very fast calculation of tables of frequency-dependent circuit parameters needed for accurate crosstalk prediction on lossy on-chip interconnections. These tables of parameters are the basis for CAD tools that perform crosstalk checking on 10K critical nets on typical microprocessor chips. A fast table generation allows for rapid incorporation of design or processing changes and transition to more advanced technologies.

US Patent:

6963204, Nov 8, 2005

Filed:

Apr 6, 2004

Appl. No.:

10/818578

Inventors:

Alina Deutsch - Chappaqua NY, US
Gerard V. Kopcsay - Yorktown Heights NY, US
Byron L. Krauter - Round Rock TX, US
Barry J. Rubin - Croton-on-Hudson NY, US
Howard H. Smith - Beacon NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G01R029/26
G01R021/00
G06F017/50

US Classification:

324613, 702 60, 716 4

Abstract:

The present invention relates to a method for analyzing the noise prediction within one or more electrical circuits, wherein the electrical circuits have a power mesh grid distribution system that feeds power levels to the electrical circuits that are connected by signal wires. After identifying a driver and receiver electrical circuit to be analyzed, a power block is generated that is associated with the driver and receiver electrical circuit by partitioning an area of a power mesh grid distribution system into a power block that can be modeled with lossy transmission line techniques. Next, signal wires situated between the driver and receiver electrical circuits are partitioned into signal blocks that can be modeled with lossy transmission line techniques. Lastly, the power blocks and signal blocks associated with the electrical circuits are analyzed in order to predict the noise performance within the electrical circuits.

US Patent:

7093206, Aug 15, 2006

Filed:

Oct 21, 2003

Appl. No.:

10/690238

Inventors:

Matthew S. Angyal - Stormville NY, US
Alina Deutsch - Chappaqua NY, US
Ibrahim M. Elfadel - Ossining NY, US
Gerard V. Kopcsay - Yorktown Heights NY, US
Barry J. Rubin - Croton-on-Hudson NY, US
Howard H. Smith - Beacon NY, US

Assignee:

International Business Machines Corp. - Armonk NY

International Classification:

G06F 17/50

US Classification:

716 1, 703 14

Abstract:

A computer aided design (CAD) system. A template generation engine generates templates from interconnect configuration files. A field solver generates high frequency passive element relationships from the templates. A circuit builder generates circuit description files from device technology models and from high frequency passive element relationships. Parameterized circuit description models may be generated for large range of sensitivity analyses. A simulator simulates circuit responses for transmission line models from the circuit description files. Interconnect configuration files may be generated by a geometry and material definition module that receives process description data from a designer.

US Patent:

7319946, Jan 15, 2008

Filed:

Oct 21, 2002

Appl. No.:

10/274861

Inventors:

Michael A. Bowen - Wallkill NY, US
Alina Deutsch - Chappaqua NY, US
Gerard V. Kopcsay - Yorktown Heights NY, US
Byron L. Krauter - Leander TX, US
Barry J. Rubin - Croton-on-Hudson NY, US
Howard H. Smith - Beacon NY, US
David J. Widiger - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 17/50
G06G 7/62
G06G 7/48

US Classification:

703 13, 703 14, 703 18, 703 3

Abstract:

New Frequency dependent RLC extraction and modeling for on chip integrity and noise verification employs:.

US Patent:

7444385, Oct 28, 2008

Filed:

Feb 25, 2002

Appl. No.:

10/468997

Inventors:

Matthias A. Blumrich - Ridgefield CT, US
Dong Chen - Croton-On-Hudson NY, US
Paul W. Coteus - Yorktown Heights NY, US
Alan G. Gara - Mount Kisco NY, US
Mark E Giampapa - Irvington NY, US
Philip Heidelberger - Cortlandt Manor NY, US
Gerard V. Kopcsay - Yorktown Heights NY, US
Todd E. Takken - Mount Kisco NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 15/16

US Classification:

709217, 709224, 710260

Abstract:

A system and method for generating global asynchronous signals in a computing structure. Particularly, a global interrupt and barrier network is implemented that implements logic for generating global interrupt and barrier signals for controlling global asynchronous operations performed by processing elements at selected processing nodes of a computing structure in accordance with a processing algorithm; and includes the physical interconnecting of the processing nodes for communicating the global interrupt and barrier signals to the elements via low-latency paths. The global asynchronous signals respectively initiate interrupt and barrier operations at the processing nodes at times selected for optimizing performance of the processing algorithms. In one embodiment, the global interrupt and barrier network is implemented in a scalable, massively parallel supercomputing device structure comprising a plurality of processing nodes interconnected by multiple independent networks, with each node including one or more processing elements for performing computation or communication activity as required when performing parallel algorithm operations. One multiple independent network includes a global tree network for enabling high-speed global tree communications among global tree network nodes or sub-trees thereof.

US Patent:

7555566, Jun 30, 2009

Filed:

Feb 25, 2002

Appl. No.:

10/468993

Inventors:

Matthias A. Blumrich - Ridgefield CT, US
Dong Chen - Croton-On-Hudson NY, US
George L. Chiu - Cross River NY, US
Thomas M. Cipolla - Cross Katonah NY, US
Paul W. Coteus - Yorktown Heights NY, US
Alan G. Gara - Mount Kisco NY, US
Mark E. Giampapa - Irvington NY, US
Philip Heidelberger - Cortlandt Manor NY, US
Gerard V. Kopcsay - Yorktown Heights NY, US
Lawrence S. Mok - Brewster NY, US
Todd E. Takken - Mount Kisco NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 15/16

US Classification:

709249, 709200, 709220, 712 1, 712 10

Abstract:

A novel massively parallel supercomputer of hundreds of teraOPS-scale includes node architectures based upon System-On-a-Chip technology, i. e. , each processing node comprises a single Application Specific Integrated Circuit (ASIC). Within each ASIC node is a plurality of processing elements each of which consists of a central processing unit (CPU) and plurality of floating point processors to enable optimal balance of computational performance, packaging density, low cost, and power and cooling requirements. The plurality of processors within a single node may be used individually or simultaneously to work on any combination of computation or communication as required by the particular algorithm being solved or executed at any point in time. The system-on-a-chip ASIC nodes are interconnected by multiple independent networks that optimally maximizes packet communications throughput and minimizes latency. In the preferred embodiment, the multiple networks include three high-speed networks for parallel algorithm message passing including a Torus, Global Tree, and a Global Asynchronous network that provides global barrier and notification functions.

US Patent:

7761687, Jul 20, 2010

Filed:

Jun 26, 2007

Appl. No.:

11/768905

Inventors:

Matthias A. Blumrich - Ridgefield CT, US
Dong Chen - Croton On Hudson NY, US
George Chiu - Cross River NY, US
Thomas M. Cipolla - Katonah NY, US
Paul W. Coteus - Yorktown Heights NY, US
Alan G. Gara - Mount Kisco NY, US
Mark E. Giampapa - Irvington NY, US
Shawn Hall - Pleasantville NY, US
Rudolf A. Haring - Cortlandt Manor NY, US
Philip Heidelberger - Cortlandt Manor NY, US
Gerard V. Kopcsay - Yorktown Heights NY, US
Martin Ohmacht - Yorktown Heights NY, US
Valentina Salapura - Chappaqua NY, US
Krishnan Sugavanam - Mahopac NY, US
Todd Takken - Brewster NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 15/173

US Classification:

712 11

Abstract:

A massively parallel supercomputer of petaOPS-scale includes node architectures based upon System-On-a-Chip technology, where each processing node comprises a single Application Specific Integrated Circuit (ASIC) having up to four processing elements. The ASIC nodes are interconnected by multiple independent networks that optimally maximize the throughput of packet communications between nodes with minimal latency. The multiple networks may include three high-speed networks for parallel algorithm message passing including a Torus, collective network, and a Global Asynchronous network that provides global barrier and notification functions. These multiple independent networks may be collaboratively or independently utilized according to the needs or phases of an algorithm for optimizing algorithm processing performance. The use of a DMA engine is provided to facilitate message passing among the nodes without the expenditure of processing resources at the node.