Giuseppe Curello

US Patent:

7101765, Sep 5, 2006

Filed:

Mar 31, 2004

Appl. No.:

10/815911

Inventors:

Giuseppe Curello - Portland OR, US
Thomas Hoffmann - Portland OR, US
Mark Armstrong - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 21/336

US Classification:

438296, 438938

Abstract:

A semiconductor device having high tensile stress. The semiconductor device comprises a substrate having a source region and a drain region. Each of the source region and the drain region includes a plurality of separated source sections and drain sections, respectively. A shallow trench isolation (STI) region is formed between two separated source sections of the source region and between two separated drain sections of the drain region. A gate stack is formed on the substrate. A tensile inducing layer is formed over the substrate. The tensile inducing layer covers the STI regions, the source region, the drain region, and the gate stack. The tensile inducing layer is an insulation capable of causing tensile stress in the substrate.

US Patent:

7129533, Oct 31, 2006

Filed:

Dec 31, 2003

Appl. No.:

10/750498

Inventors:

Cory E. Weber - Hillsboro OR, US
Mark A. Armstrong - Portland OR, US
Stephen M. Cea - Hillsboro OR, US
Giuseppe Curello - Portland OR, US
Aaron D. Lilak - Hillsboro OR, US
Max Wei - San Jose CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 29/80

US Classification:

257285, 438162, 438217, 257220

Abstract:

A method and apparatus to form a high-concentration, indium-fluorine retrograde well within a substrate. The indium-fluorine retrograde well includes an indium concentration greater than about 3E18/cm3.

US Patent:

7335959, Feb 26, 2008

Filed:

Jan 6, 2005

Appl. No.:

11/031843

Inventors:

Giuseppe Curello - Portland OR, US
Bernhard Sell - Portland OR, US
Sunit Tyagi - Portland OR, US
Chris Auth - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 29/76
H01L 29/94

US Classification:

257408, 257336, 438300

Abstract:

Embodiments of the invention provide a transistor with stepped source and drain regions. The stepped regions may provide significant strain in a channel region while minimizing current leakage. The stepped regions may be formed by forming two recesses in a substrate to result in a stepped recess, and forming the source/drain regions in the recesses.

US Patent:

7422950, Sep 9, 2008

Filed:

Dec 14, 2005

Appl. No.:

11/304351

Inventors:

Giuseppe Curello - Portland OR, US
Hemant V. Deshpande - Beaverton OR, US
Sunit Tyagi - Portland OR, US
Mark Bohr - Aloha OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 21/84

US Classification:

438300, 438151, 257E21561

Abstract:

A MOS device comprises a gate stack comprising a gate electrode disposed on a gate dielectric, a first spacer and a second spacer formed on laterally opposite sides of the gate stack, a source region proximate to the first spacer, a drain region proximate to the second spacer, and a channel region subjacent to the gate stack and disposed between the source region and the drain region. The MOS device of the invention further includes a buried oxide (BOX) region subjacent to the channel region and disposed between the source region and the drain region. The BOX region enables deeper source and drain regions to be formed to reduce transistor resistance and silicide spike defects while preventing gate edge junction parasitic capacitance.

US Patent:

7482670, Jan 27, 2009

Filed:

May 24, 2006

Appl. No.:

11/440613

Inventors:

Giuseppe Curello - Portland OR, US
Thomas Hoffmann - Portland OR, US
Mark Armstrong - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 29/00

US Classification:

257506, 257213, 257202, 257204, 257206, 257E2706, 257E27014

Abstract:

A semiconductor device having high tensile stress. The semiconductor device comprises a substrate having a source region and a drain region. Each of the source region and the drain region includes a plurality of separated source sections and drain sections, respectively. A shallow trench isolation (STI) region is formed between two separated source sections of the source region and between two separated drain sections of the drain region. A gate stack is formed on the substrate. A tensile inducing layer is formed over the substrate. The tensile inducing layer covers the STI regions, the source region, the drain region, and the gate stack. The tensile inducing layer is an insulation capable of causing tensile stress in the substrate.

US Patent:

7541239, Jun 2, 2009

Filed:

Jun 30, 2006

Appl. No.:

11/479762

Inventors:

Giuseppe Curello - Portland OR, US
Ian R. Post - Portland OR, US
Chia-Hong Jan - Portland OR, US
Mark Bohr - Aloha OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 21/8238
H01L 31/119

US Classification:

438230, 257311

Abstract:

A method of selectively forming a spacer on a first class of transistors and devices formed by such methods. The method can include depositing a conformal first deposition layer on a substrate with different classes of transistors situated thereon, depositing a blocking layer to at least one class of transistors, dry etching the first deposition layer, removing the blocking layer, depositing a conformal second deposition layer on the substrate, dry etching the second deposition layer and wet etching the remaining first deposition layer. Devices may include transistors of a first class with larger spacers compared to spacers of transistors of a second class.

US Patent:

7560780, Jul 14, 2009

Filed:

Dec 8, 2005

Appl. No.:

11/298095

Inventors:

Giuseppe Curello - Portland OR, US
Ian R. Post - Portland OR, US
Chia-Hong Jan - Portland OR, US
Sunit Tyagi - Portland OR, US
Mark Bohr - Aloha OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 29/76
H01L 29/94

US Classification:

257369, 257374, 257E2706

Abstract:

A semiconductor device and method for its fabrication are described. An active region spacer may be formed on a top surface of an isolation region and adjacent to a sidewall of an active region. In one embodiment, the active region spacer may suppress the formation of metal pipes in the active region.

US Patent:

7943468, May 17, 2011

Filed:

Mar 31, 2008

Appl. No.:

12/059455

Inventors:

Giuseppe Curello - Portland OR, US
Ian R. Post - Portland OR, US
Nick Lindert - Beaverton OR, US
Walid M. Hafez - Portland OR, US
Chia-Hong Jan - Portland OR, US
Mark T. Bohr - Aloha OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 21/336

US Classification:

438289, 438142, 438199, 438217, 438302, 438305, 438306, 438307, 438407, 438520, 438528, 438540, 438548, 438918, 257E21324, 257E21336, 257E21443, 257E21466, 257E21618

Abstract:

A semiconductor device and method to form a semiconductor device is described. The semiconductor includes a gate stack disposed on a substrate. Tip regions are disposed in the substrate on either side of the gate stack. Halo regions are disposed in the substrate adjacent the tip regions. A threshold voltage implant region is disposed in the substrate directly below the gate stack. The concentration of dopant impurity atoms of a particular conductivity type is approximately the same in both the threshold voltage implant region as in the halo regions. The method includes a dopant impurity implant technique having sufficient strength to penetrate a gate stack.