Glen David Stone

US Patent:

6389547, May 14, 2002

Filed:

Mar 18, 2000

Appl. No.:

09/531063

Inventors:

David Vernon James - Palo Alto CA
Bruce Fairman - Woodside CA
Glen David Stone - Campbell CA

Assignee:

Sony Corporation - Tokyo
Sony Electronics, Inc. - Park Ridge NJ

International Classification:

G06F 104

US Classification:

713400, 713503

Abstract:

A method and apparatus for synchronizing a bus bridge to a master clock comprising receiving a time stamp packet at an input clock register of the bus bridge, comparing the value of the input clock register to the value of an output clock register of the bus bridge, obtaining an error value of the output clock register from the comparison, and determining whether the error value is below a predetermined threshold are described.

US Patent:

6414971, Jul 2, 2002

Filed:

Jan 31, 2000

Appl. No.:

09/494753

Inventors:

David V James - Palo Alto CA
Glen D. Stone - Los Gatos CA

Assignee:

Sony Corporation - Tokyo
Sony Electronics Inc. - Park Ridge NJ

International Classification:

H04J 306

US Classification:

370519, 370486, 370386, 725 74

Abstract:

A system and method for delivering data packets in an electronic interconnect comprises a talker device that transmits one or more data packets over a transmission path to a listener device through one or more bus bridges that each couple adjacent busses in the electronic interconnect. Each data packet includes a time stamp that indicates when the corresponding data packet is scheduled for presentation to the listener device. An initial bus bridge preferably creates a marker packet that is propagated through the transmission path to record delay information corresponding to delay elements such as the intervening bus bridges. A final bus bridge may then utilize the delay information from the marker packet to update the time stamps of the data packets to thereby incorporate the total propagation delay of the transmission path.

US Patent:

6438633, Aug 20, 2002

Filed:

Apr 20, 2000

Appl. No.:

09/553304

Inventors:

Glen D. Stone - Campbell CA

Assignee:

Sony Corporation - Tokyo
Sony Electronics Inc. - Park Ridge NJ

International Classification:

G06F 1300

US Classification:

710107, 709226

Abstract:

A system for providing deterministic performance from a non-deterministic device comprises one or more nodes that perform isochronous and/or non-isochronous data transfer operations onto an input/output bus of an electronic device. A bandwidth manager preferably programs a deterministic interface with a maximum data value that is selected to prevent non-isochronous conflicts for control of the input/output bus to thereby permit successfully execution of deterministically-scheduled isochronous data transfers. The deterministic interface preferably may interrupt a non-isochronous data transfer operation whenever a data-unit total from transferred data equals the corresponding programmed maximum data value. An interrupted node may then attempt to complete the non-isochronous data transfer operation in subsequent isochronous cycles.

US Patent:

6453376, Sep 17, 2002

Filed:

Mar 9, 2000

Appl. No.:

09/521334

Inventors:

Bruce A. Fairman - Woodside CA
Scott D. Smyers - San Jose CA
Harold A. Ludtke - San Jose CA
Glen D. Stone - Campbell CA

Assignee:

Sony Corporation - Tokyo
Sony Electronics Inc. - Park Ridge NJ

International Classification:

G06F 1200

US Classification:

710240, 710107, 710113, 710119, 709223, 709224, 709226

Abstract:

A method for implementing scheduling mechanisms with selectable resource modes comprises at least one resource characterization set that includes a plurality of resource characterizations that each have resource requirements for executing a requested process. The plurality of resource characterizations may include a most mode, a best mode, and a worst mode. An allocation manager may then select a resource mode, and compare the corresponding resource requirements for the requested process to the currently-available device resources. The allocation manager may then authorize or deny the requested process depending upon whether the currently-available resources are sufficient to adequately service the resource requirements of the requested process.

US Patent:

6463489, Oct 8, 2002

Filed:

Aug 26, 1999

Appl. No.:

09/383490

Inventors:

Glen D. Stone - Campbell CA
Bruce A. Fairman - Woodside CA
Scott D. Smyers - San Jose CA

Assignee:

Sony Corporation - Tokyo
Sony Electronics Inc. - Park Ridge NJ

International Classification:

G06F 1300

US Classification:

710107, 710240

Abstract:

A system and method for effectively performing isochronous data transfers comprises a network device including an input/output (I/O) bus that is coupled to an input/output (I/O) node and an isochronous-capable network interface. The network interface and the I/O node may send requests to an arbiter for control of the I/O bus to perform a data transfer operation. In accordance with the present invention, an arbiter filter is interposed between the arbiter and both the network interface and the I/O node to filter respective requests for control of the I/O bus. The network interface advantageously provides an isochronous request to the arbiter filter to thereby de-assert conflicting requests so that the network interface may effectively perform a time-sensitive isochronous data transfer.

US Patent:

6519657, Feb 11, 2003

Filed:

Aug 8, 2000

Appl. No.:

09/634804

Inventors:

Glen David Stone - Campbell CA
David James - Palo Alto CA
Scott Smyers - San Jose CA
Jose Diaz - San Jose CA

Assignee:

Sony Electronics, Inc. - Park Ridge NJ
Sony Corporation - Tokyo

International Classification:

G06F 1338

US Classification:

710 10, 710 8, 710 15, 710306, 710311, 709222

Abstract:

A method and device for identifying that a 1394 node is actively attached to a 1394 network and indicating so to the 1394 network. In one embodiment, a border node first determines that a 1394 node is actively attached to the border node. Then, the border node sets a reserved bit in a self-identification packet, indicating the active presence of the 1394 node. Then, during the self-identification process, the border node transmits the self-identification packet into a 1394 network, indicating to all 1394 nodes in the 1394 network that there is a border node with an active connection to a 1394 node. Next, the 1394 nodes in the 1394 network of compliant devices alter their behavior for arbitration purposes, such that an 1394 network and a 1394 network may share a communication link.

US Patent:

6557067, Apr 29, 2003

Filed:

Feb 3, 2000

Appl. No.:

09/497322

Inventors:

David V. James - Palo Alto CA
Scott D. Smyers - San Jose CA
Glen D. Stone - Los Gatos CA
Bruce A. Fairman - Woodside CA

Assignee:

Sony Corporation - Tokyo
Sony Electronics Inc. - Park Ridge NJ

International Classification:

G06F 1336

US Classification:

710306, 710305, 710311, 709230, 709231, 709232, 709233, 709234, 713400, 713401

Abstract:

A system and method to effectively compensate for delays in an electronic interconnect comprises a controller that initially schedules a first transmission from a first talker device to several listener devices. The controller then schedules a second talker device to pre-roll a second transmission and selectively routes the second transmission to compensate for delays introduced by components of said electronic interconnect to thereby provide a seamless transmission stream to the several listeners.

US Patent:

6578109, Jun 10, 2003

Filed:

Jun 29, 2000

Appl. No.:

09/606813

Inventors:

Glen D. Stone - Los Gatos CA
Scott D. Smyers - San Jose CA
Bruce A. Fairman - Woodside CA

Assignee:

Sony Corporation - Tokyo
Sony Electronics Inc. - Park Ridge NJ

International Classification:

G06F 1200

US Classification:

711118, 711158, 711117, 711100, 709225, 370503, 37039561

Abstract:

A system and method for effectively implementing isochronous processor cache comprises a memory device for storing high-priority isochronous information, an isochronous cache coupled to the memory device for locally caching the isochronous information from the memory device, and a processor device for accessing and utilizing the isochronous information that is stored in the isochronous cache. The isochronous cache is reserved for storing the isochronous information, and may be reconfigured into a selectable number of cache channels of varying size that each corresponds to an associated isochronous process.