Glenn Aaron Glass

US Patent:

6949482, Sep 27, 2005

Filed:

Dec 8, 2003

Appl. No.:

10/731269

Inventors:

Anand Murthy - Portland OR, US
Boyan Boyanov - Portland OR, US
Glenn A. Glass - Beaverton OR, US
Thomas Hoffmann - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L021/00

US Classification:

438933, 438739

Abstract:

An embodiment of the invention reduces the external resistance of a transistor by utilizing a silicon germanium alloy for the source and drain regions and a nickel silicon germanium self-aligned silicide (i. e. , salicide) layer to form the contact surface of the source and drain regions. The interface of the silicon germanium and the nickel silicon germanium silicide has a lower specific contact resistivity based on a decreased metal-semiconductor work function between the silicon germanium and the silicide and the increased carrier mobility in silicon germanium versus silicon. The silicon germanium may be doped to further tune its electrical properties. A reduction of the external resistance of a transistor equates to increased transistor performance both in switching speed and power consumption.

US Patent:

7129139, Oct 31, 2006

Filed:

Dec 22, 2003

Appl. No.:

10/744195

Inventors:

Anand Murthy - Portland OR, US
Chris Auth - Portland OR, US
Glenn A. Glass - Beaverton OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 21/8234

US Classification:

438299, 438300, 438586, 438589

Abstract:

Methods and associated apparatus of forming a microelectronic structure are described. Those methods comprise providing a substrate comprising a region of higher active area density comprising source and drain recesses and a region of lower active area density comprising source and drain recesses, wherein the region of lower active area density further comprises dummy recesses, and selectively depositing a silicon alloy layer in the source, drain and dummy recesses to enhance the selectivity and uniformity of the silicon alloy deposition.

US Patent:

7195985, Mar 27, 2007

Filed:

Jan 4, 2005

Appl. No.:

11/029740

Inventors:

Anand Murthy - Portland OR, US
Glenn A. Glass - Beaverton OR, US
Andrew N. Westmeyer - Beaverton OR, US
Michael L. Hattendorf - Beaverton OR, US
Jeffrey R. Wank - Tigard OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 21/331

US Classification:

438341, 438357, 438413

Abstract:

This invention adds to the art of replacement source-drain cMOS transistors. Processes may involve etching a recess in the substrate material using one equipment set, then performing deposition in another. Disclosed is a method to perform the etch and subsequent deposition in the same reactor without atmospheric exposure. In-situ etching of the source-drain recess for replacement source-drain applications provides several advantages over state of the art ex-situ etching. Transistor drive current is improved by: (1) Eliminating contamination of the silicon-epilayer interface when the as-etched surface is exposed to atmosphere and (2) Precise control over the shape of the etch recess. Deposition may be done by a variety of techniques including selective and non-selective methods. In the case of blanket deposition, a measure to avoid amorphous deposition in performance critical regions is also presented.

US Patent:

7274055, Sep 25, 2007

Filed:

Jun 29, 2005

Appl. No.:

11/171097

Inventors:

Anand Murthy - Portland OR, US
Boyan Boyanov - Portland OR, US
Glenn A. Glass - Beaverton OR, US
Thomas Hoffmann - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 29/76
H01L 29/94
H01L 31/062
H01L 31/113
H01L 31/119

US Classification:

257288, 257 63, 257E2117, 257E21165, 257E21182, 257E21593, 257E21632

Abstract:

An embodiment of the invention reduces the external resistance of a transistor by utilizing a silicon germanium alloy for the source and drain regions and a nickel silicon germanium self-aligned silicide (i. e. , salicide) layer to form the contact surface of the source and drain regions. The interface of the silicon germanium and the nickel silicon germanium silicide has a lower specific contact resistivity based on a decreased metal-semiconductor work function between the silicon germanium and the silicide and the increased carrier mobility in silicon germanium versus silicon. The silicon germanium may be doped to further tune its electrical properties. A reduction of the external resistance of a transistor equates to increased transistor performance both in switching speed and power consumption.

US Patent:

7358547, Apr 15, 2008

Filed:

Jun 13, 2005

Appl. No.:

11/152266

Inventors:

Anand Murthy - Portland OR, US
Chris Auth - Portland OR, US
Glenn A. Glass - Beaverton OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 27/10
H01L 29/76
H01L 29/94
H01L 31/062
H01L 31/113
H01L 31/119
H01L 29/00

US Classification:

257202, 257368, 257506

Abstract:

Methods and associated apparatus of forming a microelectronic structure are described. Those methods comprise providing a substrate comprising a region of higher active area density comprising source and drain recesses and a region of lower active area density comprising source and drain recesses, wherein the region of lower active area density further comprises dummy recesses, and selectively depositing a silicon alloy layer in the source, drain and dummy recesses to enhance the selectivity and uniformity of the silicon alloy deposition.

US Patent:

7402872, Jul 22, 2008

Filed:

Jan 20, 2006

Appl. No.:

11/336160

Inventors:

Anand S. Murthy - Portland OR, US
Glenn A. Glass - Beaverton OR, US
Andrew N. Westmeyer - Beaverton OR, US
Michael L. Hattendorf - Beaverton OR, US
Tahir Ghani - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 29/76
H01L 29/94
H01L 31/062
H01L 31/113

US Classification:

257382, 257408, 257412

Abstract:

A method is described for manufacturing an n-MOS semiconductor transistor. Recesses are formed in a semiconductor substrate adjacent a gate electrode structure. Silicon is embedded in the recesses via a selective epitaxial growth process. The epitaxial silicon is in-situ alloyed with substitutional carbon and in-situ doped with phosphorus. The silicon-carbon alloy generates a uniaxial tensile strain in the channel region between the source and drain, thereby increasing electron channel mobility and the transistor's drive current. The silicon-carbon alloy decreases external resistances by reducing contact resistance between source/drain and silicide regions and by reducing phosphorous diffusivity, thereby permitting closer placement of the transistor's source/drain and channel regions.

US Patent:

7479432, Jan 20, 2009

Filed:

Dec 21, 2006

Appl. No.:

11/643523

Inventors:

Anand Murthy - Portland OR, US
Glenn A. Glass - Beaverton OR, US
Andrew N. Westmeyer - Beaverton OR, US
Michael L. Hattendorf - Beaverton OR, US
Jeffrey R. Wank - Tigard OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 27/108

US Classification:

438300, 438299, 438303, 438E29277, 438E21106

Abstract:

This invention adds to the art of replacement source-drain cMOS transistors. Processes may involve etching a recess in the substrate material using one equipment set, then performing deposition in another. Disclosed is a method to perform the etch and subsequent deposition in the same reactor without atmospheric exposure. In-situ etching of the source-drain recess for replacement source-drain applications provides several advantages over state of the art ex-situ etching. Transistor drive current is improved by: (1) Eliminating contamination of the silicon-epilayer interface when the as-etched surface is exposed to atmosphere and (2) Precise control over the shape of the etch recess. Deposition may be done by a variety of techniques including selective and non-selective methods. In the case of blanket deposition, a measure to avoid amorphous deposition in performance critical regions is also presented.

US Patent:

7678631, Mar 16, 2010

Filed:

Jun 6, 2006

Appl. No.:

11/448247

Inventors:

Anand Murthy - Portland OR, US
Glenn Glass - Beaverton OR, US
Michael L. Hattendorf - Beaverton OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 21/336

US Classification:

438197, 438300, 438607, 257E2143

Abstract:

A method to form a strain-inducing three-component epitaxial film is described. In one embodiment, the strain-inducing epitaxial film is formed by a multiple deposition/etch step sequence, followed by an amorphizing dopant impurity-implant and, finally, a kinetically-driven crystallization process. In one embodiment, the charge-neutral lattice-substitution atoms are smaller and present in greater concentration than the charge-carrier dopant impurity atoms.