Golam R Chowdhury

US Patent:

6980056, Dec 27, 2005

Filed:

Nov 13, 2000

Appl. No.:

09/711770

Inventors:

Mark Alexander - Austin TX, US
Krishnan Subramonium - Austin TX, US
Golam Chowdhury - Austin TX, US
Kartika Prihadi - Austin TX, US
Bryan Cope - Austin TX, US

Assignee:

Cirrus Logic, Inc. - Austin TX

International Classification:

H03G003/10
H03G003/30

US Classification:

330284, 381120, 333 81 R

Abstract:

An attenuator includes a first stage having a first operational amplifier and a tapped resistor. Tapped resistor has an input for receiving input data, an output coupled to an output of first operational amplifier , and a plurality of taps for selectively presenting a sequence of voltages to a noninverting input of first operational amplifier. Each of these sequences of voltages corresponds to an attenuation step such that first stage steps the attenuation produced by the attenuator from an intermediate value to a predetermined ending value. A second stage includes a second operational amplifier and a tapped resistor. Tapped resistor includes an input for receiving analog data from first stage , an output coupled to an output of second operational amplifier , and a plurality of taps for selectively presenting a sequence of voltages to a noninverting input of operational amplifier. Each of the sequence of voltages corresponds to an attenuation step, a second stage stepping the attenuation from a predetermined starting value to the intermediate value.

US Patent:

7164311, Jan 16, 2007

Filed:

Sep 30, 2004

Appl. No.:

10/954887

Inventors:

Golam R. Chowdhury - Austin TX, US
Douglas R. Holberg - Wimberly TX, US

Assignee:

Silicon Laboratories Inc. - Austin TX

International Classification:

H03K 5/00

US Classification:

327553, 327552

Abstract:

A system and method for providing a tunable GMC filter is disclosed wherein a transconducted element having an attenuator in a feedback loop therewith is allowed to oscillate at a first oscillation frequency. An input to the filter enables tuning of the oscillation frequency to a pre-determined frequency.

US Patent:

7187319, Mar 6, 2007

Filed:

Sep 29, 2005

Appl. No.:

11/238931

Inventors:

Golam R. Chowdhury - Austin TX, US

Assignee:

Silicon Laboratories Inc. - Austin TX

International Classification:

H03M 1/34

US Classification:

341163, 341161

Abstract:

A sampling network comprises analog comparator for comparing an analog voltage to a plurality of successive voltage inputs. A plurality of capacitors are connected in parallel with a first end of each of the capacitors coupled to the first input of the analog comparator to provide one of the successive voltage inputs. A first plurality of switches includes one switch associated with each of the plurality of capacitors to connect an input voltage to the second end of the capacitor. A bulk of a switch of the first plurality of switches is connected to the input voltage while the input voltage is being sampled and to a power supply voltage while the reference voltage is being sampled. A second plurality of switches is in parallel with the first plurality of switches and further includes one switch connected to each of the plurality of capacitors. The second plurality of switches connect a reference voltage to a second end of the capacitor. A bulk of a switch of the second plurality of switches is connected to the reference voltage while the reference voltage is being sampled and to the power supply voltage while the input voltage is being sampled.

US Patent:

7199746, Apr 3, 2007

Filed:

Dec 19, 2005

Appl. No.:

11/311508

Inventors:

Golam R. Chowdhury - Austin TX, US
Douglas Piasecki - Austin TX, US

Assignee:

Silicon Laboratories Inc. - Austin TX

International Classification:

H03M 1/12

US Classification:

341172, 341118, 341120

Abstract:

The method is described for selecting capacitors from a capacitor array for each bit of a SAR ADC. The process involves selecting a group of capacitors from the capacitor array and determining a weight of the selected group of capacitors. A determination is made if the weights of the selected group of capacitors are substantially equal to their desired values. If the weights are substantially equal to their desired values, the selected group of capacitors is associated with each bit of the SAR ADC. If the weights are not substantially equal to their desired values, a next group of capacitors from the capacitor array is selected for the bits. This process of selecting a group of capacitors and determining their weights is repeated until determined weight for a group of capacitors equals or is closest to the desired values.

US Patent:

7373533, May 13, 2008

Filed:

Sep 30, 2005

Appl. No.:

11/241277

Inventors:

Douglas F. Pastorello - Hudson NH, US
Golam R. Chowdhury - Austin TX, US

Assignee:

Silicon Laboratories - Dallas TX

International Classification:

G06F 1/26

US Classification:

713300, 326 80

Abstract:

The present invention comprises a microcontroller unit including a processor for generating a power down signal. Control logic generates a hold signal responsive to the power down signal. A voltage regulator provides a regulated voltage responsive to an input voltage and powers down responsive to the power down signal. At least one digital device powered by the regulated voltage enters a powered down mode responsive to the voltage regulator entering the powered down state. The at least one digital device provides at least one digital output signal that is provided to an input/output cell. The input/output cell also is connected to receive a hold signal. The input/output cell maintains a last state of the digital output signal responsive to the hold signal when the at least one digital device enters the powered down state.

US Patent:

7382181, Jun 3, 2008

Filed:

Jan 16, 2007

Appl. No.:

11/623686

Inventors:

Golam R. Chowdhury - Austin TX, US
Douglas R. Holberg - Wimberly TX, US

Assignee:

Silicon Laboratories Inc. - Austin TX

International Classification:

H03K 5/00

US Classification:

327553, 327552

Abstract:

A system and method for providing a tunable GMC filter is disclosed wherein a transconducted element having an attenuator in a feedback loop therewith is allowed to oscillate at a first oscillation frequency. An input to the filter enables tuning of the oscillation frequency to a pre-determined frequency.

US Patent:

7441131, Oct 21, 2008

Filed:

Sep 30, 2005

Appl. No.:

11/240923

Inventors:

Douglas F. Pastorello - Hudson NH, US
Douglas Holberg - Wimberly TX, US
William Gene Durbin - Austin TX, US
Golam R. Chowdhury - Austin TX, US

Assignee:

Silicon Laboratories Inc. - Austin TX

International Classification:

G06F 1/00
G05F 1/00

US Classification:

713300, 713322, 327540

Abstract:

A microcontroller unit includes a processor for generating a first control signal to start a comatose mode of operation for the microcontroller unit. Control logic responsive to the first control signal generates an enable signal at a first level and the control logic is further responsive to a second control signal for generating the enable signal at a second level. A voltage regulator generates regulated voltage from an input voltage. The voltage regulator shuts down to provide a zero volt regulated voltage responsive to the enable signal at the first level and powers up to provide a regulated voltage at an operating level responsive to the enable signal at the second level.

US Patent:

7746262, Jun 29, 2010

Filed:

Dec 19, 2005

Appl. No.:

11/311509

Inventors:

Golam R. Chowdhury - Austin TX, US
Douglas S. Piasecki - Austin TX, US
Bruce Del Signore - Hollis NH, US
Kevin Kwak - Westford MA, US

Assignee:

Silicon Laboratories Inc. - Austin TX

International Classification:

H03M 1/34

US Classification:

341163, 341161

Abstract:

A method for coding a digital to analog converter of a successive approximation register analog to digital converter includes the steps of first switching capacitors associated with a bit from ground to a reference voltage. Next, a determination is made of whether a logical value of the bit is a first or a second value. If the logical value is the first value, capacitors associated with a next bit are switched from ground to a reference voltage. If the logical value is the second value, one half of the capacitors associated with the bit currently connected are switched from the reference voltage to ground.