Gordon J Robbins

US Patent:

6395991, May 28, 2002

Filed:

Jul 29, 1996

Appl. No.:

08/688073

Inventors:

Robert Charles Dockerty - Austin TX
Ronald Maurice Fraga - Pflugerville TX
Ciro Neal Ramirez - Round Rock TX
Sudipta Kumar Ray - Wappingers Falls NY
Gordon Jay Robbins - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H05K 103

US Classification:

174252, 174260, 361760, 361773, 361779

Abstract:

Structure and method for reinforcing a solder column grid array attachment of a ceramic or the like substrate to a printed circuit board, the reinforcement providing support for a heat sink which is bonded or affixed by pressure to a structural element of the substrate. In one form, the invention involves the concurrent formation of materially larger solder columns along the perimeter of the substrate in conjunction with the array of thin electrically interconnecting solder columns on the substrate. The reinforcing and electrical signal columns are thereafter aligned and attached by solder reflow to a corresponding pattern of pads on the printed circuit board. The heat sink is thermally connected to a structural element of the substrate by bonding or mechanical compression. Stresses in the solder columns caused by heat sink compressive forces or vibration induced flexing are materially decreased without adding complex or unique manufacturing operations.

US Patent:

6457089, Sep 24, 2002

Filed:

Oct 21, 1999

Appl. No.:

09/422368

Inventors:

Gordon J. Robbins - Austin TX
Donald Norman Senzig - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1300

US Classification:

710306

Abstract:

The present invention discloses a microprocessor bus structure that enables a processor chip to be designed with optional unidirectional or bi-directional I/O buses. The processor is designed with separate input and output bus internal to the chip. A gating network is coupled to these processor uni-directional busses that allows the chip to have an alternate externally wired bus structure. For the lowest cost and lowest performance only one set of bidirectional bus lines are wired external to the chip. These lines have a parallel driver and receiver with appropriate gating to allow the bus to be either in the send or receive mode. The signals from the processor uni-directional input and output buses are wired via appropriate gating to create a single bi-directional bus. For high performance operation where higher cost for higher bandwidth is justified, the bidirectional bus is gated to be a device output only bus and the alternate device input bus is gated to the processor input bus creating a true uni-directional bus structure. The bus enable line is wired to the appropriated stated depending on the wired microprocessor bus structure.

US Patent:

20030023889, Jan 30, 2003

Filed:

Jul 26, 2001

Appl. No.:

09/915661

Inventors:

Harm Hofstee - Austin TX, US
Gordon Robbins - Austin TX, US

International Classification:

G06F001/26
G06F001/28
G06F001/30

US Classification:

713/322000, 307/152000, 307/117000, 307/097000

Abstract:

A transitioning of power dissipation in a processing device () is coordinated with the operation of a cooling system () for the processing device. A power transitioning arrangement () transitions power dissipation in the processing device () between a high power level and a relatively lower low power level. In conjunction with a transitioning of the processing device power level, the cooling system () is placed in either a high or low thermal impedance state to reduce the rate at which the temperature of the data processing device () and related elements change in response to the change in power dissipated by the processing device. Transitioning the power dissipation in the processing device () may be accomplished by gradually varying the clock rate for the device, by changing the clock rate to various processing elements in the device at different times, and/or by changing the instruction issue rate in the device.

US Patent:

20040201970, Oct 14, 2004

Filed:

Apr 10, 2003

Appl. No.:

10/411419

Inventors:

Paul Harvey - Austin TX, US
Harm Hofstee - Austin TX, US
James Kahle - Austin TX, US
Gordon Robbins - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H05K007/02

US Classification:

361/760000

Abstract:

Disclosed is an apparatus which shows the use of an inwardly disposed set of Ctype I/O connections to an integrated circuit chip over and above the typical peripherally disposed set of I/O connections which use wire type connections between the chip and other circuitry of a substrate upon which the chip is mounted. The inwardly disposed set of connections may be used to provide a direct connection to an optional ancillary chip having a corresponding set of I/O connection points. Such a construction not only increases the number of possible I/O connections, but additionally increases the bandwidth of communications between the directly connected chips.

US Patent:

57570795, May 26, 1998

Filed:

Dec 21, 1995

Appl. No.:

8/577677

Inventors:

Michael McAllister - Clintondale NY
James McDonald - Newburgh NY
Eric Daniel Perfecto - Poughkeepsie NY
Chandrika Prasad - Wappingers Falls NY
Keshav Prasad - San Jose CA
Gordon J. Robbins - Austin TX
Madhavan Swaminathan - Marietta GA
George Eugene White - Marietta GA

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2348
H01L 2352
H01L 2940
H01L 2358

US Classification:

257776

Abstract:

A multi-layer thin film structure having defined repair lines thereon and a method for repairing interconnections in the multi-layer thin film structure (MLTF) and/or making engineering charges (EC) are provided. The method comprises determining any interconnection defects in the MLTF at a thin film layer adjacent the top metal layer of the structure, using lithography, e. g. , direct write expose technology, to define the top surface connections needed to repair the interconnections and/or make EC's, and forming the top surface metallization and repair lines using additive or substractive metallization techniques.

US Patent:

57470952, May 5, 1998

Filed:

Feb 14, 1997

Appl. No.:

8/800945

Inventors:

Michael McAllister - Clintondale NY
Eric Daniel Perfecto - Poughkeepsie NY
James McDonald - Newburgh NY
Keshav Prasad - San Jose CA
Gordon J. Robbins - Austin TX
Chandrika Prasad - Wappingers Falls NY
Madhavan Swaminathan - Marietta GA
George Eugene White - Marietta GA

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

B05D 512

US Classification:

427 8

Abstract:

A multi-layer thin film structure having defined repair lines thereon and a method for repairing interconnections in the multi-layer thin film structure (MLTF) and/or making engineering charges (EC) are provided. The method comprises determining any interconnection defects in the MLTF at a thin film layer adjacent the top metal layer of the structure, using lithography, e. g. , direct write expose technology, to define the top surface connections needed to repair the interconnections and/or make EC's, and forming the top surface metallization and repair lines using additive or substractive metallization techniques.

US Patent:

39860574, Oct 12, 1976

Filed:

Jun 30, 1975

Appl. No.:

5/592153

Inventors:

Edward Baxter Eichelberger - Purdy Station NY
Gordon Jay Robbins - Wappingers Falls NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03K 3286
H03K 1908
H03K 1934
H03K 1938

US Classification:

307289

Abstract:

Disclosed is a high performance logically hazard-free latch circuit compatible with TTL technology. The occurrence of both a clock and data signal provides an inverted data output signal at the output node which is fed back to the base electrode of a multi-emitter transistor. The output node then remains latched at the desired logic level until the occurrence of a subsequent clock signal. Also disclosed are techniques for improving the capabilities of the latch and for accepting additional clock and data inputs. The polarity-hold latch circuit disclosed herein is advantageously implemented in semiconductor integrated circuit technology.

US Patent:

52088790, May 4, 1993

Filed:

Oct 18, 1991

Appl. No.:

7/779428

Inventors:

Antonio R. Gallo - Pleasant Valley NY
Gordon J. Robbins - Wappingers Falls NY
Robert R. Shaw - Poughkeepsie NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G02B 610
G02B 612
G02B 636

US Classification:

385 14

Abstract:

Disclosed is an optical signal distribution system. The system comprises an electronic substrate, at least one optical component and at least one optical waveguide on but distinct from the electronic substrate for carrying an optical signal to or from the optical component.