Gordon A Shaw

US Patent:

7114240, Oct 3, 2006

Filed:

Nov 12, 2003

Appl. No.:

10/706531

Inventors:

Daniel L. Baseman - Minneapolis MN, US
Lonny L. Berg - Elk River MN, US
Romney R. Katti - Maple Grove MN, US
Daniel S. Reed - Maple Plain MN, US
Gordon A. Shaw - Plymouth MN, US
Wei D. Z. Zou - Minnetonka MN, US

Assignee:

Honeywell International, Inc. - Morristown NJ

International Classification:

G11B 5/127
H04R 31/00

US Classification:

2960315, 2960307, 2960313, 2960314, 2960316, 2960318, 216 22, 216 48, 216 65, 360316, 36032411, 36032412, 3603242, 427127, 427128, 451 5, 451 41

Abstract:

In a method of fabricating a giant magnetoresistive (GMR) device a plurality of magnetoresistive device layers is deposited on a first silicon nitride layer formed on a silicon oxide layer. An etch stop is formed on the magnetoresistive device layers, and a second layer of silicon nitride is formed on the etch stop. The magnetoresistive device layers are patterned to define a plurality of magnetic bits having sidewalls. The second silicon nitride layer is patterned to define electrical contact portions on the etch stop in each magnetic bit. The sidewalls of the magnetic bits are covered with a photoresist layer. A reactive ion etch (RIE) process is used to etch into the first silicon nitride and silicon oxide layers to expose electrical contacts. The photoresist layer and silicon nitride layers protect the magnetoresistive layers from exposure to oxygen during the etching into the silicon oxide layer.

US Patent:

7183042, Feb 27, 2007

Filed:

Nov 12, 2003

Appl. No.:

10/706067

Inventors:

Romney R. Katti - Maple Grove MN, US
Paul S. Fechner - Plymouth MN, US
Gordon A. Shaw - Plymouth MN, US
Daniel S. Reed - Maple Plain MN, US
David W. Zou - Minnetonka MN, US

Assignee:

Honeywell International Inc. - Morristown NJ

International Classification:

G03F 7/20

US Classification:

430320, 430313, 430314, 430316, 430318

Abstract:

In a process of making a magnetoresistive memory device, a mask layout is produced by use of any suitable design tool. The mask layout is laid out in grids having a central grid forming a central section and grids forming bit end sections, and the grids of the bit end sections are rectangles. A mask is made by use of the mask layout, and the mask has stepped bit ends. The mask is used to make a magnetic storage layer having tapered bit ends, to make a magnetic sense layer having tapered bit ends, and to make a non-magnetic layer having tapered bit ends. The non-magnetic layer is between the magnetic sense layer and the magnetic storage layer.

US Patent:

7383626, Jun 10, 2008

Filed:

Aug 22, 2006

Appl. No.:

11/508671

Inventors:

Daniel L. Baseman - Minneapolis MN, US
Lonny L. Berg - Elk River MN, US
Romney R. Katti - Maple Grove MN, US
Daniel S. Reed - Maple Plain MN, US
Gordon A. Shaw - Plymouth MN, US
Wei D. Z. Zou - Minnetonka MN, US

Assignee:

Honeywell International Inc. - Morristown NJ

International Classification:

G11B 5/127
H04R 31/00

US Classification:

2960315, 2960307, 2960313, 2960314, 2960316, 2960318, 216 22, 216 48, 216 65, 360316, 36032411, 36032412, 3603242, 427127, 427128, 451 5, 451 41

Abstract:

In a method of fabricating a giant magnetoresistive (GMR) device a plurality of magnetoresistive device layers is deposited on a first silicon nitride layer formed on a silicon oxide layer. An etch stop is formed on the magnetoresistive device layers, and a second layer of silicon nitride is formed on the etch stop. The magnetoresistive device layers are patterned to define a plurality of magnetic bits having sidewalls. The second silicon nitride layer is patterned to define electrical contact portions on the etch stop in each magnetic bit. The sidewalls of the magnetic bits are covered with a photoresist layer. A reactive ion etch (RIE) process is used to etch into the first silicon nitride and silicon oxide layers to expose electrical contacts. The photoresist layer and silicon nitride layers protect the magnetoresistive layers from exposure to oxygen during the etching into the silicon oxide layer.

US Patent:

7732287, Jun 8, 2010

Filed:

May 2, 2006

Appl. No.:

11/415703

Inventors:

Paul S. Fechner - Plymouth MN, US
Gordon A. Shaw - Plymouth MN, US
Eric E. Vogt - Maple Grove MN, US

Assignee:

Honeywell International Inc. - Morristown NJ

International Classification:

H01L 21/336

US Classification:

438296, 438221, 438427, 257E21548

Abstract:

A method of forming a body-tie. The method includes forming the body-tie during an STI scheme of an SOI process. During the STI scheme, a first trench is formed. The first trench stops before a buried oxide layer of the SOI substrate. The first trench may determine a height of body tie that is shared between at least two FETs. A second trench may also be formed within the first trench. The second trench stops in the SOI substrate. The second trench defines the location and shape of a body-tie. Once the location and shape of the body-tie are defined, an oxide is deposited above the body-tie. The deposited oxide prevents certain implants from entering the body tie. By preventing these implants, a source and a drain implant may be self-aligned to the source and drain areas without requiring the use of the photoresist mask to shield the body tie regions from the source and drain implant.

US Patent:

8299506, Oct 30, 2012

Filed:

Dec 1, 2009

Appl. No.:

12/628889

Inventors:

Andy Peczalski - Eden Prarie MN, US
Robert E. Higashi - Shorewood MN, US
Gordon Alan Shaw - Plymouth MN, US
Thomas Keyser - Plymounth MN, US

Assignee:

Honeywell International Inc. - Morristown NJ

International Classification:

H01L 29/84

US Classification:

257254, 257508, 257351, 257690, 438 51, 438 52, 438702

Abstract:

A method of forming CMOS circuitry integrated with MEMS devices includes bonding a wafer to a top surface layer having contacts formed to CMOS circuitry. A handle wafer is then removed from one of the top or bottom surfaces of the CMOS circuitry, and MEMS devices are formed in a remaining silicon layer.

US Patent:

20080233704, Sep 25, 2008

Filed:

Mar 23, 2007

Appl. No.:

11/690379

Inventors:

Paul S. Fechner - Plymouth MN, US
Gordon A. Shaw - Plymouth MN, US

Assignee:

HONEYWELL INTERNATIONAL INC. - Morristown NJ

International Classification:

H01L 21/20

US Classification:

438381

Abstract:

A resistor capacitor structure and a method of fabrication. A resistor capacitor structure provides a capacitance between at least two nodes within a microelectronic circuit. A bottom plate of the resistor capacitor structure comprises a resistance layer, which in turn provides a resistance path between an additional node within the circuit. The resistor capacitor structure may be formed on top or within interlevel dielectric layers. The resistance layer, alternatively, may be used to fill a cavity located between interlevel dielectric layers and accordingly provide a resistance path between the interlevel dielectric layers.

US Patent:

62251783, May 1, 2001

Filed:

Jan 2, 1990

Appl. No.:

7/466709

Inventors:

Gordon A. Shaw - Plymouth MN
Curtis H. Rahn - Plymouth MN
Cheisan Yue - Roseville MN
Todd A. Randazzo - Savage MN

Assignee:

Honeywell Inc. - Morristown NJ

International Classification:

H01L 21336
H01L 21338

US Classification:

438308

Abstract:

A process for oxidizing the silicon layer into a device-isolating field oxide having a radiation-hardened reduced bird's beak. An angled and rotated field implant prior to oxidation is used to increase the doping concentration in the edge region of the MOS transistors to compensate for boron leaching during oxidation. The field oxide is grown at a low temperature by high pressure oxidation which increases total dose hardness by making a silicon-rich oxide film.

US Patent:

52121089, May 18, 1993

Filed:

Dec 13, 1991

Appl. No.:

7/807307

Inventors:

Michael S. Liu - Bloomington MN
Gordon A. Shaw - Plymouth MN
Jerry Yue - Roseville MN

Assignee:

Honeywell Inc. - Minneapolis MN

International Classification:

H01L 2170
H01L 2700

US Classification:

437 60

Abstract:

A method for fabricating polysilicon resistors of intermediate high value for use as cross-coupling or =ingle event upset (SEU) resistors in memory cells. A thin polysilicon film is implanted with arsenic ions to produce a predetermined resistivity. The thin film is then implanted with fluorine ions to stabilize the grain boundaries and thereby the barrier height. Reducing the variation in barrier height from run to run of wafers allows the fabrication of reproducible SEU resistors.