Grady S Waldo from 5549 Broadwing Way, Boise, ID 83716, age 61, Phone: 2083441088

Resumes

Grady Waldo

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Location:

Boise, ID

Industry:

Semiconductors

Us Patents

Method Of Forming Trench Isolation Within A Semiconductor Substrate
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US Patent:

7205245, Apr 17, 2007
Filed:

Aug 10, 2005
Appl. No.:

11/200632
Inventors:

Janos Fucsko - Boise ID, US
Grady S. Waldo - Boise ID, US
Kevin J. Torek - Meridian ID, US
Li Li - Meridian ID, US
Assignee:

Micron Technology, Inc. - Boise ID
International Classification:

H01L 21/461
H01L 21/302
H01L 21/8283
US Classification:

438757, 438218, 438745, 438749, 438747, 438750, 438584, 438738, 438791, 438424, 257E21546
Abstract:

A method of etching silicon nitride substantially selectively relative to an oxide of aluminum includes providing a substrate comprising silicon nitride and an oxide of aluminum. The silicon nitride and the oxide is exposed to an etching solution comprising HF and an organic HF solvent under conditions effective to etch the silicon nitride substantially selectively relative to the oxide. Other aspects and implementations are contemplated.

Method Of Removing Silicon From A Substrate
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US Patent:

7316981, Jan 8, 2008
Filed:

Dec 28, 2006
Appl. No.:

11/648272
Inventors:

Janos Fucsko - Boise ID, US
Grady S. Waldo - Boise ID, US
Assignee:

Micron Technology, Inc. - Boise ID
International Classification:

H01L 21/465
US Classification:

438753, 216 99
Abstract:

A wet etching method of removing silicon from a substrate includes depositing a layer comprising silicon in elemental form over a substrate. The layer is exposed to an aqueous liquid etching solution comprising a hydroxide and a fluoride, and having a pH of at least 10, under conditions and for a period of time effective to etch the elemental silicon from the substrate. Wet etching can be employed in methods of forming trench isolation, and in other methods. Other aspects and implementations are contemplated.

Etch Compositions And Methods Of Processing A Substrate
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US Patent:

7491650, Feb 17, 2009
Filed:

Jul 27, 2005
Appl. No.:

11/191685
Inventors:

Janos Fucsko - Boise ID, US
Grady S. Waldo - Boise ID, US
Joseph Wiggins - Boise ID, US
Prashant Raghu - Boise ID, US
Assignee:

Micron Technology, Inc. - Boise ID
International Classification:

H01L 21/302
US Classification:

438745, 216 83
Abstract:

The invention includes an etchant composition containing isopropyl alcohol and one or more of HF, NHF and tetramethyl ammonium fluoride (TMAF). The invention encompasses a method of processing a substrate. A substrate is provided which has a first material containing at least one of polysilicon, monocrystalline silicon and amorphous silicon, and a second material. The substrate is exposed to an etch composition which comprises isopropyl alcohol and at least one of HF, NHF and TMAF. The invention includes a method of processing a semiconductor construction including providing a construction which has a capacitor electrode material and an oxide material along at least a portion of the capacitor electrode material. At least some of the oxide material is removed by isotropic etching utilizing an etchant composition comprising isopropyl alcohol.

Low Temperature Process For Polysilazane Oxidation/Densification
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US Patent:

7521378, Apr 21, 2009
Filed:

Jul 1, 2004
Appl. No.:

10/883191
Inventors:

Janos Fucsko - Boise ID, US
Li Li - Meridian ID, US
Grady S Waldo - Boise ID, US
Assignee:

Micron Technology, Inc. - Boise ID
International Classification:

H01L 21/31
H01L 21/469
US Classification:

438781, 438799, 257E21489, 427 964, 427344
Abstract:

Semiconductor devices, structures and systems that utilize a polysilazane-based silicon oxide layer or fill, and methods of making the oxide layer are disclosed. In one embodiment, a polysilazane solution is deposited on a substrate and processed with ozone in a wet oxidation at low temperature to chemically modify the polysilazane material to a silicon oxide layer.

Low Temperature Process For Polysilazane Oxidation/Densification
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US Patent:

7557420, Jul 7, 2009
Filed:

Dec 29, 2005
Appl. No.:

11/321511
Inventors:

Janos Fucsko - Boise ID, US
Li Li - Meridian ID, US
Grady S Waldo - Boise ID, US
Assignee:

Micron Technology, Inc. - Boise ID
International Classification:

H01L 21/76
H01L 29/00
US Classification:

257499, 257501, 257E21553, 257E27108
Abstract:

Semiconductor devices, structures and systems that utilize a polysilazane-based silicon oxide layer or fill, and methods of making the oxide layer are disclosed. In one embodiment, a polysilazane solution is deposited on a substrate and processed with ozone in a wet oxidation at low temperature to chemically modify the polysilazane material to a silicon oxide layer.

Etch Compositions And Methods Of Processing A Substrate
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US Patent:

7629266, Dec 8, 2009
Filed:

Mar 1, 2007
Appl. No.:

11/680916
Inventors:

Janos Fucsko - Boise ID, US
Grady S. Waldo - Boise ID, US
Joseph Wiggins - Boise ID, US
Prashant Raghu - Boise ID, US
Assignee:

Micron Technology, Inc. - Boise ID
International Classification:

H01L 21/302
US Classification:

438745, 438689, 438704, 257E21219, 257E21223, 257E21309, 216 83, 216108, 216109, 252 791, 252 792
Abstract:

The invention includes an etchant composition containing isopropyl alcohol and one or more of HF, NHF and tetramethyl ammonium fluoride (TMAF). The invention encompasses a method of processing a substrate. A substrate is provided which has a first material containing at least one of polysilicon, monocrystalline silicon and amorphous silicon, and a second material. The substrate is exposed to an etch composition which comprises isopropyl alcohol and at least one of HF, NHF and TMAF. The invention includes a method of processing a semiconductor construction including providing a construction which has a capacitor electrode material and an oxide material along at least a portion of the capacitor electrode material. At least some of the oxide material is removed by isotropic etching utilizing an etchant composition comprising isopropyl alcohol.

Method Of Substantially Uniformly Etching Non-Homogeneous Substrates
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US Patent:

7699998, Apr 20, 2010
Filed:

Aug 22, 2005
Appl. No.:

11/209059
Inventors:

Janos Fucsko - Boise ID, US
Grady Waldo - Boise ID, US
Bob Carstensen - Boise ID, US
Satish Bedge - Cupertino CA, US
Assignee:

Micron Technology, Inc. - Boise ID
International Classification:

H01L 21/302
US Classification:

216 83, 216 97, 216 99, 216101, 216108, 216109, 134 2, 134902, 438745, 438906
Abstract:

A method of substantially uniformly etching oxides from non-homogeneous substrates is provided. The method utilizes a substantially non-aqueous etchant including an organic solvent and a fluorine-containing compound. The fluorine containing compound may include HF, HF:NHF, (NH)HF, or TMAF:HF and mixtures thereof. The etchant may be applied to chemically non-homogeneous layers such as shallow trench isolation fill oxide layers, or to layers having a non-homogeneous composition or density at different depths within the layers, such as spin-on-glass or spin-on-dielectric films.

Method Of Forming Trench Isolation
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US Patent:

7811897, Oct 12, 2010
Filed:

Oct 18, 2006
Appl. No.:

11/583633
Inventors:

Janos Fucsko - Boise ID, US
Grady S. Waldo - Boise ID, US
Assignee:

Micron Technology, Inc. - Boise ID
International Classification:

H01L 21/465
US Classification:

438430, 438692, 438753
Abstract:

A wet etching method of removing silicon from a substrate includes depositing a layer comprising silicon in elemental form over a substrate. The layer is exposed to an aqueous liquid etching solution comprising a hydroxide and a fluoride, and having a pH of at least 10, under conditions and for a period of time effective to etch the elemental silicon from the substrate. Wet etching can be employed in methods of forming trench isolation, and in other methods. Other aspects and implementations are contemplated.