Greg G Hess

US Patent:

20220269617, Aug 25, 2022

Filed:

May 9, 2022

Appl. No.:

17/662500

Inventors:

- Cupertino CA, US
Ben D. Jarrett - Austin TX, US
Edward M. McCombs - Austin TX, US
Greg M. Hess - Mountain View CA, US

International Classification:

G06F 12/10
G06F 12/06
G11C 11/419
G06F 17/16
G11C 7/10
G11C 5/14
G11C 8/06

Abstract:

A method and apparatus for storing and accessing sparse data is disclosed. A sparse array circuit may receive information indicative of a request to perform a read operation on a memory circuit that includes multiple banks. The sparse array circuit may compare an address included in the received information to multiple entries that correspond to address locations in the memory circuit that store sparse data. In response to a determination that that the address matches a particular entry, the sparse array may generate one or more control signals that may disable the read operation, and cause a data control circuit to transmits the sparse data pattern.

US Patent:

20200320013, Oct 8, 2020

Filed:

Jun 22, 2020

Appl. No.:

16/908182

Inventors:

- Cupertino CA, US
Ben D. Jarrett - Austin TX, US
Edward M. McCombs - Austin TX, US
Greg M. Hess - Mountain View CA, US

International Classification:

G06F 12/10
G06F 12/06
G11C 11/419
G06F 17/16
G11C 7/10
G11C 5/14
G11C 8/06

Abstract:

A method and apparatus for storing and accessing sparse data is disclosed. A sparse array circuit may receive information indicative of a request to perform a read operation on a memory circuit that includes multiple banks. The sparse array circuit may compare an address included in the received information to multiple entries that correspond to address locations in the memory circuit that store sparse data. In response to a determination that that the address matches a particular entry, the sparse array may generate one or more control signals that may disable the read operation, and cause a data control circuit to transmits the sparse data pattern.

US Patent:

20190095339, Mar 28, 2019

Filed:

Sep 6, 2018

Appl. No.:

16/124166

Inventors:

- Cupertino CA, US
Ben D. Jarrett - Austin TX, US
Edward M. McCombs - Austin TX, US
Greg M. Hess - Mountain View CA, US

International Classification:

G06F 12/10
G06F 17/16
G11C 11/419
G06F 12/06

Abstract:

A method and apparatus for storing and accessing sparse data is disclosed. A sparse array circuit may receive information indicative of a request to perform a read operation on a memory circuit that includes multiple banks. The sparse array circuit may compare an address included in the received information to multiple entries that correspond to address locations in the memory circuit that store sparse data. In response to a determination that that the address matches a particular entry, the sparse array may generate one or more control signals that may disable the read operation, and cause a data control circuit to transmits the sparse data pattern.